Visible to Intel only — GUID: xvz1691560429875
Ixiasoft
4.3.1. General-Purpose Register File
4.3.2. Arithmetic Logic Unit
4.3.3. Multipy and Divide Units
4.3.4. Floating-Point Unit
4.3.5. Custom Instruction
4.3.6. Reset and Debug Signals
4.3.7. Control and Status Registers
4.3.8. Exception Controller
4.3.9. Interrupt Controller
4.3.10. Memory and I/O Organization
4.3.11. RISC-V based Debug Module
4.3.12. Error Correction Code (ECC)
Visible to Intel only — GUID: xvz1691560429875
Ixiasoft
3.1.1. Pipelined
FPGA Used | fMAX (MHz) | Logic Size (ALM) | Architecture Performance | |
---|---|---|---|---|
DMIPS/MHz Ratio | CoreMark/MHz Ratio | |||
Intel® Cyclone® 10 | 283 | 1151 | 0.567 | 0.400 |
Intel® Arria® 10 | 301 | 1155 | ||
Intel® Stratix® 10 | 342 | 1354 | ||
Intel Agilex® 7 | 423 | 1334 |
Parameter | Settings/Description | |
---|---|---|
Intel® Quartus® Prime seed | Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Pro Edition software version 23.4. | |
Device speed grade | Fastest speed grade from each Intel FPGA device family. | |
Defined peripherals |
|
|
Toolchain | Version |
|
Compiler configuration |
|
FPGA Used | fMAX (MHz) | Logic Size | Architecture Performance | |
---|---|---|---|---|
DMIPS/MHz Ratio | CoreMark/MHz Ratio | |||
Intel® Cyclone® IV E | 107 | 2831 (LE) | 0.650 | 0.441 |
Intel® Cyclone® V | 145 | 1253 (ALM) | ||
Intel® Arria® V | 145 | 1222 (ALM) | ||
Intel® Arria® V GZ | 264 | 1215 (ALM) | ||
Intel® Stratix® V | 304 | 1199 (ALM) | ||
Intel® Cyclone® 10 LP | 135 | 2848 (LE) | ||
Intel® Arria® 10 | 290 | 1132 (ALM) | ||
Intel® MAX® 10 | 123 | 2864 (LE) |
Parameter | Settings/Description | |
---|---|---|
Intel® Quartus® Prime seed | Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Standard Edition software version 23.1. | |
Device speed grade | Fastest speed grade from each Intel FPGA device family. | |
Defined peripherals |
|
|
Toolchain | Version |
|
Compiler configuration |
|
Intel uses the same Intel® Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. The compiler settings are:
- Superior Performance with Maximum Placement Effort in Intel® Quartus® Prime Pro Edition software.
- High Performance Effort in Intel® Quartus® Prime Standard Edition software.
Note: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.