AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

Download PDF
ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.3. DisplayPort Hot Plug Detect (HPD)

The DisplayPort sink device drives the HPD signal using 3.3V TTL signal level. The upstream DisplayPort source device monitors the HPD signal.

To prevent the HPD signal from floating when not connected, tie to GND with a >100K ohm resistor in both the DisplayPort Intel® FPGA IP source and sink devices.

Note: The voltage level of the HPD pin uses 3.3 V TTL. FPGA I/Os that are not tolerant with 3.3V TTL require a level shifter.
Level Two Title