F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 12/22/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

1.4. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved Mode (number of segments = 1)The following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.4.
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 18478.0 40,639 7,564 28
10.3125 12 58294.5 112,252 18,681 73
12.5 4 18481.3 40,684 7,569 28
8 37750.3 76,015 13,523 52
10 47808.5 93,995 16,019 61
12 58266.0 112,189 18,759 73
25.78125 4 18612.6 41,553 7,617 28
6 29562.0 63,525 11,398 52
8 38116.6 76,908 14,007 52
10 53091.3 110,085 18,160 100
12 63052.5 126,513 21,446 100
PAM4 FGT 53.125 2 18151.7 45,039 8,527 28
2 (with EFIFO) 18510.3 45,236 8,638 28
4 36751.2 83,237 16,148 52
4 (with EFIFO) 37592.9 84,433 15,641 52
6 60517.4 136,969 23,420 100
6 (with EFIFO) 61636.0 137,769 23,811 100
8 80670.5 177,959 30,453 100
8 (with EFIFO) 82167.4 179,367 30,594 100
10 105753.8 227,598 37,050 121
10 (with EFIFO) 107625.9 230,559 38,043 121
12 141500.0 304,524 45,692 196
12 (with EFIFO) 143865.1 309,472 45,972 196
56.25 10 106484.2 229,354 37,548 121
10 (with EFIFO) 107578.4 229,142 36,828 121
12 142536.9 306,186 47,216 196
12 (with EFIFO) 143599.8 308,833 46,910 196
FHT 106.25 1 (with EFIFO) 18468.7 45,404 8,503 28
2 (with EFIFO) 37473.6 83,948 16,005 52
3 (with EFIFO) 61577.8 137,897 23,519 100
4 (with EFIFO) 82162.9 179,124 30,516 100
Table 5.  Resource Utilization for Packet ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.4.
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 18495.0 40,729 7,537 28
10.3125 12 58294.4 112,202 18,785 73
12.5 4 18482.8 40,744 7,535 28
8 37784.1 75,966 13,389 52
10 47851.5 94,068 15,933 61
12 58216.3 112,370 18,579 73
25.78125 4 18645.2 41,281 7,859 28
6 29565.7 63,094 11,726 52
8 38091.3 76,914 14,065 52
10 52977.6 109,323 18,730 100
12 63210.0 126,493 21,482 100
PAM4 FGT 53.125 2 18182.1 45,007 8,546 28
2 (with EFIFO) 18532.7 45,358 8,532 28
4 36754.6 83,600 15,722 52
4 (with EFIFO) 37548.9 84,560 15,626 52
6 60434.4 136,383 24,019 100
6 (with EFIFO) 61600.9 137,756 23,585 100
8 80501.3 178,084 30,445 100
8 (with EFIFO) 82110.2 178,809 30,890 100
10 105799.3 227,061 36,728 121
10 (with EFIFO) 107758.2 230,544 37,259 121
12 141541.2 303,897 46,265 196
12 (with EFIFO) 143726.1 308,787 46,556 196
56.25 10 106365.8 228,371 38,033 121
10 (with EFIFO) 107411.7 231,408 37,383 121
12 142430.8 307,167 46,172 196
12 (with EFIFO) 143569.3 308,983 46,471 196
FHT 106.25 1 (with EFIFO) 18489.0 45,137 8,762 28
2 (with EFIFO) 37503.4 84,137 15,967 52
3 (with EFIFO) 61562.4 137,609 23,705 100
4 (with EFIFO) 82051.4 179,062 30,661 100
Table 6.  Resource Utilization for Interlaken Look-aside ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.4.
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 13665.5 30622 5591 0
10.3125 12 43797.0 81743 15177 0
12.5 4 13618.3 30734 5570 0
8 27920.5 55011 10266 0
10 35831.6 69854 12631 0
12 43831.8 81617 15420 0
25.78125 4 13646.8 30812 5787 0
6 20624.9 43096 8346 0
8 27948.3 55073 10713 0
10 35651.3 69970 13410 0
12 43868.0 81901 15917 0
PAM4 FGT 53.125 2 13183.9 34385 6661 0
2 (with EFIFO) 13603.7 34899 6513 0
4 26977.4 62559 12097 0
4 (with EFIFO) 27747.6 63004 12290 0
6 42255.1 92678 18043 0
6 (with EFIFO) 43093.1 93578 18212 0
FHT 106.25 1 (with EFIFO) 13571.3 34844 6592 0
2 (with EFIFO) 27712.2 62936 12276 0
3 (with EFIFO) 43116.3 93398 18099 0
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