F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 12/22/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.12.22 22.4 6.0.0
  • Features
    • Serial lane configuration bullet point in General Features updated
    • Per lane data rate bullet point in General Features updated
    • Per lane data rate bullet point in Line-side Features updated
    • IP Supported Combinations of Number of Lanes and Data Rates table updated with new 56.25 Gbps column
    • IP Theoretical Raw Aggregate Bandwidth table updated
  • Performance and Resource Utilization
    • Resource Utilization for Interleaved Mode table updated
    • Resource Utilization for Packet Mode table updated
    • Resource Utilization for Interlaken Look-aside Mode table updated
  • Round-trip Latency: Round-trip Latency Numbers table updated
  • Parameter Settings: Main: General Table following rows updated:
    • PMA Type: FHT changed to FGT default setting
    • Number of lanes: 16, 20, 24 supported values added
    • Data Rate: 28.125 supported value added
  • Transmit User Interface Signals: itx_num_valid, itx_sob, itx_sop, itx_din_words rows updated
  • Receive User Interface Signals: irx_num_valid, irx_sob, irx_sop, irx_dout_words rows updated
2022.09.26 22.3 5.0.0
  • Added a new section: Device Speed Grade Support.
  • Added the clock frequency for mac_clkin in section: Clock and Reset Interface Signals.
  • Added new signal: mac_pll_locked.
  • Corrected the I/O direction for itx_ch0_xon and itx_ch1_xon.
2022.06.21 22.2 4.1.0
  • Added the FHT PMA support for PAM4 variants.
  • Updated the sections with FHT PMA information: Features and System PLL Configuration.
  • Updated the Resource Utilization and Round-trip Latency numbers.
  • Added information about the IP-XACT file generation in section: Specifying the IP Core Parameters and Options.
  • Added note for Enable EFIFO support.
  • Added signal availability for Interlaken and Interlaken Look-aside mode in section: Interface Signals.
2022.03.28 22.1 4.0.0
  • Added support for the Interlaken Look-aside mode for all variants.
  • Updated the Resource Utilization numbers.
  • Removed support for the ModelSim* SE simulator.
2022.01.14 21.4 3.1.0
  • Added support for the Cadence* Xcelium* simulator.
  • Added support for the Interlaken Look-aside mode for three variants:
    • 6 x 53.125G
    • 12 x 12.5G
    • 12 x 25.78125G
  • Added support for new lane rate combinations. For more information, refer to Table: IP Supported Combinations of Number of Lanes and Data Rate.
  • Updated the Resource Utilization numbers.
  • Added new parameters:
    • Enable Interlaken Look-aside mode
    • Enable debug endpoint for Datapath and PMA Avalon® memory-mapped interface
2021.10.04 21.3 3.0.0
  • Added support for new lane rate combinations. For more information, refer to Table: IP Supported Combinations of Number of Lanes and Data Rate.
  • Updated the reset signals in sections: IP Reset and Clock and Reset Interface Signals.
2021.06.21 21.2 2.0.0 Initial release.
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