Visible to Intel only — GUID: bag1615577054701
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2.4.1. System PLL Configuration
For Interlaken, the NRZ mode is supported without FEC while the PAM4 mode is supported with FEC.
Instantiate the F-Tile Reference and System PLL Clocks Intel FPGA IP for your F-Tile Interlaken Intel® FPGA IP design with the following parameters:
Parameters | Value for NRZ Mode | Value for PAM4 Mode |
---|---|---|
Mode of System PLL (syspll_mod_<m>) |
User Configuration | User Configuration |
Refclk source (syspll_refclk_src_<m>) |
RefClk #<n> | RefClk #<n> |
Output frequency (syspll_freq_mhz_<m>) |
Any frequency | 830.078125 MHz |
Enable Refclk #<n> for FGT PMA (refclk_fgt_output_enable_<n>) |
Yes | Yes |
Refclk frequency #<n> (refclk_fgt_freq_mhz_<n>) |
User desired refclk frequency | User desired refclk frequency |
Figure 5. Port Connection between F-Tile Reference and System PLL Clocks Intel FPGA IP and F-Tile Interlaken Intel® FPGA IP