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Ixiasoft
Visible to Intel only — GUID: aoz1492212055938
Ixiasoft
3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs
ATX PLL-to-ATX PLL Spacing Guidelines
For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 7 ATX PLLs apart (skip 6).
For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GX channels, they must be placed 4 ATX PLLs apart (skip 3).
For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GT channels, they must be placed 3 ATX PLLs apart (skip 2).
For two ATX PLLs providing the serial clock for PCIe*/PIPE Gen3, they must be placed 4 ATX PLL apart (skip 3).
- One of the ATX PLL re-calibration process is triggered.
- The other channel (that is clocked by another ATX PLL) is in data transmission mode.
ATX PLL-to-fPLL Spacing Guidelines
- When ATX PLL VCO frequency and fPLL VCO frequency is within 50MHz.
- ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/OC192/STM64, 10G GPON or protocol that has jitter integration start range <1MHz and data rate > 3Gbps.
- fPLL user re-calibration process is triggered.
- ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/OC192/STM64, 10G GPON or protocol that has jitter integration start range <1MHz and data rate > 3Gbps.