3.12. PLLs and Clock Networks Revision History

Arria® 10 Transceiver PHY User Guide

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ID 683617

Date 4/01/2024

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3.12. PLLs and Clock Networks Revision History

Document Version	Changes
2021.06.10	Added the PCS Bonding Channels Placement Restrictions section.
2021.01.29	Made the following change: To implement fPLL to fPLL cascading, set the destination (downstream) fPLL bandwidth to Low.
2019.05.13	Made the following change: Renamed Altera Debug Master Endpoint (ADME) to Native PHY DebugMaster Endpoint (NPDME).
2018.06.15	Made the following change: For fPLL IP Core, added OTN_direct, SATA_Gen3 and HDMI to the range for Protocol Mode.
2017.11.06	Made the following changes: Updated the "ATX PLL-to-ATX PLL Spacing Guidelines" section with GT channels information. Added note "Sourcing reference clock from a cascaded PLL output, global clock or core clock network will introduce additional jitter to transmit PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria® 10 PLL reference clock?" for more details." Added guidance for jitter compliance for data rates >10 Gbps in the following sections: "fPLL" "CMU PLL" "Input Reference Clock Sources"
2016.10.31	Made the following change: New section Unused/Idle Clock Line Requirements added.
2016.05.02	Updated ATX PLL, fPLL and CMU PLL parameters. Updated ATX PLL and fPLL ports. Added new parameters and ports when fPLL is used in core mode. Provided additional details for ATX PLL and fPLL fractional mode usage in the "Delta Sigma Modulator" section. Added a new section describing "ATX PLL multi-profile and embedded reconfiguration".
2016.02.11	Made the following changes: Updated the optimal performance placement guidelines for ATX PLL VCO frequencies. Updated placement recommendations for different protocols - OTU2e, OTU2, OC-192, 6G and 12G SDI. Updated the "FPGA Fabric - Transceiver Interface Clocking" figure. Updated the maximum data rate to 25.8 Gbps.
2015.12.18	Made the following changes: Updated the “PLL Cascading” figure. Updated the "Dedicated Reference Clock Pins" in the "Input Reference Clock Sources" section.
2015.11.02	Made the following changes: Updated ATX PLL, CMU PLL and fPLL Configuration Options, Parameters and Settings. Updated ATX PLL placement in figures and examples. Clarified PLL to PLL cascade support. Created TX PLL Recommendations based on datarates. Updated ATX PLL, fPLL and CMU PLL Quartus settings. Added details and figures for the fPLL driving the fabric use cases. Updated PLL Feedback and Cascading Clock Network figure. Updated steps to implement PLL cascading.
2015.05.11	Made the following changes: Updated ATX PLL, CMU PLL and FPLL Configuration Options, Parameters and Settings. Modified Transmit PLLs Data Rate Range in Arria 10 Devices. Increased xN clock network channel span. Added ATX PLL to fPLL cascading details.
2014.12.15	Made the following changes: Added a note about PLL cascading support in ACDS 14.1 version of Quartus II software. Corrected the minimum data rate supported by ATX PLL in Table: Transmit PLLs in Arria 10 Devices. Corrected the error in PLL output frequency range for ATX PLL and CMU PLL IP cores. Corrected the PLL reference clock frequency range for ATX PLL IP core. Added a note about jitter performance in Input Reference Clock Sources section. Updated the Mix and Match Design Example figure to indicate that MCGB is used in the example. Changed the minimum data rate supported by the PLLs to 1 Gbps.
2014.08.15	Made the following changes: Changed the maximum data rate for GT channels to 25.8 Gbps. Changed figure "Arria 10 PLLs and Clock Networks" to indicate channel 0,1,3, and 5 have only the CDR PLL. Updated figure "x1 Clock Lines" to indicate that the channel PLL of channel 1 and channel 4 can be used as CMU PLL or as a CDR. Updated ATX PLL, fPLL, and CMU PLL section with a clarification about input reference clock frequency stability at device power-up. Updated Instantiating ATX PLL, fPLL, and CMU PLL topics with new IP instantiation flow. Updated ATX PLL and fPLL architecture block diagrams to show global clock or core clock as an input reference clock. Updated ATX PLL IP section with 14.0 A10 release changes Added fractional mode support. Added embedded debug parameters in table ATX PLL Dynamic Reconfiguration. Updated fPLL IP section with 14.0A10 release changes Removed "fPLL -Clock Switch over Parameter and Settings" table. Updated table "fPLL Parameter and Settings". Added embedded debug parameters in table "fPLL - Dynamic Reconfiguration Parameters and Settings". Removed Number of auxiliary MCGB clock input ports from fPLL IP parameters. Added global clock or core clock as an input reference clock source. Added a new section for Global Clock or Core Clock as an Input Reference Clock. Updated figure "Input Reference Clock Sources". Updated Dedicated Reference Clock Pins section "Dedicated Reference Clock Pins". Added a connection to indicate that dedicated refclk pins can drive the reference clock network. Removed a wrong connection from the diagram. Updated xN Clock Lines section with maximum channel span limitations and added a exception for QPI protocols. Added a new image in the FPGA Fabric-Transceiver Interface Clocking section. Added a new section for Channel Bonding describing PMA bonding, PMA and PCS bonding in detail. Removed xN Clock Network Data Rate Restrictions table. Updated chapter to indicate Arria 10 Transceivers support fPLL to fPLL, fPLL to ATX PLL, and fPLL to CMU PLL cascading. Updated Using PLLs and Clock Networks section Changed MegaWizard references to IP Catalog and Parameter Editor. Updated the valid configurations for PLL IP and Native PHY IP per 14.0A10 release change. Removed Table "xN Clock Network Data Rate Restrictions". Updated the chapter to indicate Arria 10 transceivers support to fPLL to fPLL, fPLL to ATX PLL, and fPLL to CMU PLL cascading.
2013.12.02	Initial release.