Visible to Intel only — GUID: nik1398706866631
Ixiasoft
Visible to Intel only — GUID: nik1398706866631
Ixiasoft
2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC
Parameter |
Range |
---|---|
Message level for rule violations |
error, warning |
Transceiver Configuration Rule |
10GBASE-R 10GBASE-R 1588 10GBASE-R with KR FEC |
Transceiver mode |
TX / RX Duplex, TX Simplex, RX Simplex |
Number of data channels |
1 to 96 |
Data rate |
10312.5 Mbps |
Enable datapath and interface reconfiguration |
Off |
Enable simplified data interface |
On Off |
Parameter |
Range |
---|---|
TX channel bonding mode |
Not bonded |
TX local clock division factor |
1, 2, 4, 8 |
Number of TX PLL clock inputs per channel |
1, 2, 3, 4 |
Initial TX PLL clock input selection |
0 |
Parameter |
Range |
---|---|
Number of CDR reference clocks |
1 to 5 |
Selected CDR reference clock |
0 to 4 |
Selected CDR reference clock frequency 35 |
156.25 MHz, 322.265625 MHz, and 644.53125 MHz |
PPM detector threshold |
100, 300, 500, 1000 |
CTLE adaptation mode | manual |
DFE adaptation mode | adaptation enabled, manual, disabled |
Number of fixed DFE taps | 3, 7, 11 |
Parameter |
Range |
---|---|
Enhanced PCS/PMA interface width |
32, 40, 64
Note: 10GBASE-R with KR-FEC allows 64 only.
|
FPGA fabric/Enhanced PCS interface width |
66 |
Enable Enhanced PCS low latency mode | On Off |
Enable RX/TX FIFO double-width mode |
Off |
TX FIFO mode |
|
TX FIFO partially full threshold |
11 |
TX FIFO partially empty threshold |
2 |
RX FIFO mode |
|
RX FIFO partially full threshold |
23 |
RX FIFO partially empty threshold |
2 |
Parameter |
Range |
---|---|
Enable TX 64B/66B encoder |
On |
Enable RX 64B/66B decoder |
On |
Enable TX sync header error insertion |
On Off |
Parameter |
Range |
---|---|
Enable TX scrambler (10GBASE-R / Interlaken) |
On |
TX scrambler seed (10GBASE-R / Interlaken) |
0x03ffffffffffffff |
Enable RX descrambler (10GBASE-R / Interlaken) |
On |
Parameter |
Range |
---|---|
Enable RX block synchronizer |
On |
Enable rx_enh_blk_lock port |
On Off |
Parameter |
Range |
---|---|
Enable TX data polarity inversion |
On Off |
Enable RX data polarity inversion |
On Off |
Parameter |
Range |
---|---|
Enable dynamic reconfiguration |
On Off |
Share reconfiguration interface |
On Off |
Enable Native PHY Debug Master Endpoint |
On Off |
De-couple reconfig_waitrequest from calibration |
On Off |
Parameter |
Range |
---|---|
Configuration file prefix |
— |
Generate SystemVerilog package file |
On Off |
Generate C header file |
On Off |
Generate MIF (Memory Initialization File) |
On Off |
Parameter |
Range |
---|---|
Generate parameter documentation file |
On Off |