Visible to Intel only — GUID: nik1398706836649
Ixiasoft
Visible to Intel only — GUID: nik1398706836649
Ixiasoft
2.5.5. Native PHY IP Parameter Settings for Interlaken
Parameter |
Value |
---|---|
Message level for rule violations |
error warning |
Transceiver configuration rules |
Interlaken |
PMA configuration rules | basic |
Transceiver mode |
TX / RX Duplex TX Simplex RX Simplex |
Number of data channels |
1 to 96 |
Data rate |
Up to 17.4 Gbps for GX devices (Depending on Enhanced PCS to PMA interface width selection) |
Enable datapath and interface reconfiguration |
On / Off |
Enable simplified data interface |
On / Off |
Provide separate interface for each channel |
On / Off |
Parameter |
Value |
---|---|
TX channel bonding mode |
Not bonded PMA-only bonding PMA and PCS bonding |
PCS TX channel bonding master |
If TX channel bonding mode is set to PMA and PCS bonding, then: Auto, 0, 1, 2, 3 through [Number of data channels – 1] |
Actual PCS TX channel bonding master |
If TX channel bonding mode is set to PMA and PCS bonding, then: 0, 1, 2, 3 through [Number of data channels – 1] |
TX local clock division factor |
If TX channel bonding mode is not bonded, then: 1, 2, 4, 8 |
Number of TX PLL clock inputs per channel |
If TX channel bonding mode is not bonded, then: 1, 2, 3, 4 |
Initial TX PLL clock input selection |
0 |
Enable tx_pma_clkout port |
On / Off |
Enable tx_pma_div_clkout port |
On / Off |
tx_pma_div_clkout division factor |
When Enable tx_pma_div_clkout port is On, then: Disabled, 1, 2, 33, 40, 66 |
Enable tx_pma_elecidle port |
On / Off |
Enable tx_pma_qpipullup port (QPI) |
Off |
Enable tx_pma_qpipulldn port (QPI) |
Off |
Enable tx_pma_txdetectrx port (QPI) |
Off |
Enable tx_pma_rxfound port (QPI) |
Off |
Enable rx_seriallpbken port |
On / Off |
Parameter |
Value |
---|---|
Number of CDR reference clocks |
1 to 5 |
Selected CDR reference clock |
0 to 4 |
Selected CDR reference clock frequency |
Select legal range defined by the Quartus Prime software |
PPM detector threshold |
100, 300, 500, 1000 |
CTLE adaptation mode |
manual, |
DFE adaptation mode |
adaptation enabled, manual, disabled |
Number of fixed dfe taps |
3, 7, 11 |
Enable rx_pma_clkout port |
On / Off |
Enable rx_pma_div_clkout port |
On / Off |
rx_pma_div_clkout division factor |
When Enable rx_pma_div_clkout port is On, then: Disabled, 1, 2, 33, 40, 66 |
Enable rx_pma_clkslip port |
On / Off |
Enable rx_pma_qpipulldn port (QPI) |
Off |
Enable rx_is_lockedtodata port |
On / Off |
Enable rx_is_lockedtoref port |
On / Off |
Enable rx_set_locktodata and rx_set_locktoref ports |
On / Off |
Enable rx_seriallpbken port |
On / Off |
Enable PRBS verifier control and status ports |
On / Off |
Parameter |
Value |
---|---|
Enhanced PCS / PMA interface width |
32, 40, 64 |
FPGA fabric / Enhanced PCS interface width |
67 |
Enable 'Enhanced PCS' low latency mode |
Allowed when the PMA interface width is 32 and preset variations for data rate is 10.3125 Gbps or 6.25 Gbps; otherwise Off |
Enable RX/TX FIFO double-width mode |
Off |
TX FIFO mode |
Interlaken |
TX FIFO partially full threshold |
8 to 15 |
TX FIFO partially empty threshold |
1 to 8 |
Enable tx_enh_fifo_full port |
On / Off |
Enable tx_enh_fifo_pfull port |
On / Off |
Enable tx_enh_fifo_empty port |
On / Off |
Enable tx_enh_fifo_pempty port |
On / Off |
RX FIFO mode |
Interlaken |
RX FIFO partially full threshold |
from 10-29 (no less than pempty_threshold+8) |
RX FIFO partially empty threshold |
2 to 10 |
Enable RX FIFO alignment word deletion (Interlaken) |
On / Off |
Enable RX FIFO control word deletion (Interlaken) |
On / Off |
Enable rx_enh_data_valid port |
On / Off |
Enable rx_enh_fifo_full port |
On / Off |
Enable rx_enh_fifo_pfull port |
On / Off |
Enable rx_enh_fifo_empty port |
On / Off |
Enable rx_enh_fifo_pempty port |
On / Off |
Enable rx_enh_fifo_del port (10GBASE-R) |
Off |
Enable rx_enh_fifo_insert port (10GBASE-R) |
Off |
Enable rx_enh_fifo_rd_en port |
On |
Enable rx_enh_fifo_align_val port (Interlaken) |
On / Off |
Enable rx_enh_fifo_align_clr port (Interlaken) |
On |
Parameter |
Value |
---|---|
Enable Interlaken frame generator |
On |
Frame generator metaframe length |
5 to 8192 (Intel recommends a minimum metaframe length of 128) |
Enable frame generator burst control |
On |
Enable tx_enh_frame port |
On |
Enable tx_enh_frame_diag_status port |
On |
Enable tx_enh_frame_burst_en port |
On |
Parameter |
Value |
---|---|
Enable Interlaken frame synchronizer |
On |
Frame synchronizer metaframe length |
5 to 8192 (Intel recommends a minimum metaframe length of 128) |
Enable rx_enh_frame port |
On |
Enable rx_enh_frame_lock port |
On / Off |
Enable rx_enh_frame_diag_status port |
On / Off |
Parameter |
Value |
---|---|
Enable Interlaken TX CRC-32 generator |
On |
Enable Interlaken TX CRC-32 generator error insertion |
On / Off |
Enable Interlaken RX CRC-32 checker |
On |
Enable rx_enh_crc32_err port |
On / Off |
Parameter |
Value |
---|---|
Enable TX scrambler (10GBASE-R / Interlaken) |
On |
TX scrambler seed (10GBASE-R / Interlaken) |
0x1 to 0x3FFFFFFFFFFFFFF |
Enable RX descrambler (10GBASE-R / Interlaken) |
On |
Parameter |
Value |
---|---|
Enable Interlaken TX disparity generator |
On |
Enable Interlaken RX disparity checker |
On |
Enable Interlaken TX random disparity bit |
On / Off |
Parameter |
Value |
---|---|
Enable RX block synchronizer |
On |
Enable rx_enh_blk_lock port |
On / Off |
Parameter |
Value |
---|---|
Enable TX data bitslip |
Off |
Enable TX data polarity inversion |
On / Off |
Enable RX data bitslip |
Off |
Enable RX data polarity inversion |
On / Off |
Enable tx_enh_bitslip port |
Off |
Enable rx_bitslip port |
Off |
Parameter |
Value |
---|---|
Enable dynamic reconfiguration |
On / Off |
Share reconfiguration interface |
On / Off |
Enable Native PHY Debug Master Endpoint |
On / Off |
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE |
On / Off |
Enable capability registers |
On / Off |
Set user-defined IP identifier: |
0 to 255 |
Enable control and status registers |
On / Off |
Enable prbs soft accumulators |
On / Off |
Parameter |
Value |
---|---|
Configuration file prefix |
— |
Generate SystemVerilog package file |
On / Off |
Generate C header file |
On / Off |
Generate MIF (Memory Initialization File) |
On / Off |
Include PMA analog settings in configuration files |
On / Off |
Parameter |
Value |
---|---|
Enable multiple reconfiguration profiles |
On / Off |
Enable embedded reconfiguration streamer | On / Off |
Generate reduced reconfiguration files | On / Off |
Number of reconfiguration profiles | 1 to 8 |
Selected reconfiguration profile | 1 to 7 |