Visible to Intel only — GUID: nik1398707015136
Ixiasoft
Visible to Intel only — GUID: nik1398707015136
Ixiasoft
2.10.1.1. How to Use NativeLink to Specify a ModelSim* Simulation
Complete the following steps to specify the directory path and testbench settings for your simulator:
- On the Tools menu, click Options, and then click EDA Tool Options.
- Browse to the directory for your simulator. The following table lists the directories for supported simulators:
Table 225. Simulator Path Simulator
Path
Mentor Graphics* ModelSim® - Intel FPGA Edition
<drive>:\<simulator install path>\win32aloem (Windows)
/<simulator install path>/bin (Linux*)
- On the Assignments menu, click Settings.
- In the Category list, under EDA Tool Settings select Simulation.
- In the Tool name list, select your simulator.
Note: ModelSim refers to ModelSim SE and PE. These simulators use the same commands as QuestaSim. ModelSim® - Intel FPGA Edition refers to ModelSim® - Intel FPGA Edition Starter Edition and ModelSim® - Intel FPGA Edition Subscription Edition.
- In the Output directory, browse to the directory for your output files.
- To map illegal HDL characters, turn on Map illegal HDL characters.
- To filter netlist glitches , turn on Enable glitch filtering.
- Complete the following steps to specify additional options for NativeLink automation:
- Turn on Compile test bench.
- Click Test Benches.
The Test Benches dialog box appears.
- Click New.
- Under Create new test bench settings, for Test bench name type the test bench name. For Top level module in the test bench, type the top-level module name. These names should match the actual test bench module names.
- Select Use test bench to perform VHDL timing simulation and specify the name of your design instance under Design instance name in test bench.
- Under the Simulation period, turn on Run simulation until all vector stimuli are used.
- Under Test bench and simulation files, select your test bench file from your folder. Click Add.
- Click OK.