Visible to Intel only — GUID: nfa1420705162994
Ixiasoft
Visible to Intel only — GUID: nfa1420705162994
Ixiasoft
2.6.5.5.1. Clock and Reset Signals
Signal Name | Direction | Width | Description |
---|---|---|---|
Clock signals | |||
tx_clkout | Output |
1 |
GMII TX clock, derived from tx_serial_clk[1:0]. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE. |
rx_clkout | Output |
1 |
GMII RX clock, derived from tx_serial_clk[1:0]. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE. |
csr_clk | Input |
1 |
Clock for the control and status Avalon® memory-mapped interface. Intel recommends 125 – 156.25 MHz for this clock. |
xgmii_tx_coreclkin | Input | 1 | XGMII TX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 10M/100M/1G/2.5G/5G/10G (USXGMII) mode. Synchronous to tx_serial_clk with zero ppm. |
xgmii_rx_coreclkin | Input | 1 | XGMII RX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 10M/100M/1G/2.5G/5G/10G (USXGMII) mode. |
latency_measure_clk | Input | 1 | Sampling clock for measuring the latency of the 16-bit GMII datapath. This clock operates at 80 MHz and is available only when the IEEE 1588v2 feature is enabled. |
tx_serial_clk | Input |
1-3 | Serial clock from transceiver PLLs.
|
rx_cdr_refclk | Input |
1 |
125 MHz RX CDR reference clock for 1GbE and 2.5GbE |
rx_cdr_refclk_1 | Input | 1 | RX CDR reference clock for 10GbE. The frequency of this clock can be either 322.265625 MHz or 644.53125 MHz, as specified by the Reference clock frequency for 10 GbE (MHz) parameter setting. |
rx_pma_clkout | Output | 1 | Recovered clock from CDR, operates at the following frequency:
10M/100M/1G/2.5G/5G/10G (USXGMII) speed mode:
Other speed modes:
|
Reset signals | |||
reset | Input |
1 |
Active-high global reset. Assert this signal to trigger an asynchronous global reset. |
tx_analogreset | Input |
1 |
Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the analog block on the TX path. |
tx_digitalreset | Input |
1 |
Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the TX path. |
rx_analogreset | Input |
1 |
Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the receiver CDR. |
rx_digitalreset | Input |
1 |
Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the RX path. |