Intel® Stratix® 10 H-tile and L-tile Avalon® Memory-mapped Hard IP for PCI Express* Design Example User Guide

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ID 683616
Date 3/07/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Design Components 1.2. Hardware and Software Requirements 1.3. Directory Structure 1.4. Generating the Design Example 1.5. Simulating the Design Example 1.6. Compiling the Design Example and Programming the Device 1.7. Installing the Linux Kernel Driver 1.8. Running the Design Example Application
2. Design Example Description x
2.1. Functional Description for the DMA Design Example 2.2. Serial Data Signals
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide x
A.1. Intel® Stratix® 10 H-tile and L-tile Avalon® memory mapped Hard IP for PCI Express* Design Example User Guide Revision History
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

1.8. Running the Design Example Application

  1. Navigate to ./software/user/example under the design example directory.
  2. Compile the design example application:
    $ make
  3. Run the test:

    $ sudo ./intel_fpga_pcie_link_test

    You can run the Intel® FPGA IP PCIe* link test in manual or automatic mode.

    • In automatic mode, the application automatically selects the device. The test selects the Intel® Stratix® 10 PCIe* device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
    • In manual mode, the test queries you for the bus, device, and function number and BAR.
    For the Intel® Stratix® 10 GX Development Kit, you can determine the BDF by typing the following command:

    $ lspci -d 1172

  4. Here are sample transcripts for automatic and manual modes: 
    Intel FPGA PCIe Link Test - Automatic Mode
Version 2.0
0: Automatically select a device
1: Manually select a device
***************************************************
>0
Opened a handle to BAR 0 of a device with BDF 0x100
***************************************************
0: Link test - 100 writes and reads
1: Write memory space
2: Read memory space
3: Write configuration space
4: Read configuration space
5: Change BAR
6: Change device
7: Enable SR-IOV
8: Do a link test for every enabled virtual function
   belonging to the current device
9: Perform DMA
10: Quit program
***************************************************
> 0
Doing 100 writes and 100 reads . . 
Number of write errors:     0
Number of read errors:      0
Number of DWORD mismatches: 0
    Intel FPGA PCIe Link Test - Manual Mode
Version 1.0
0: Automatically select a device
1: Manually select a device
***************************************************
> 1
Enter bus number:
> 1
Enter device number:
> 0
Enter function number:
> 0
BDF is 0x100
Enter BAR number (-1 for none):
> 4
Opened a handle to BAR 4 of a device with BDF 0x100
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