1.1. Serial Peripheral Interface
The SPI bus has only one master, which is connected to many slaves.
Altera device acts as one of the slaves to the SPI master device.
Figure 2. Timing Diagram for SPI
| Signal | Direction | Function |
|---|---|---|
| SS | Input (active low) | Slave select |
| SCLK | Input | SPI cloc |
| MISO | Output | Master-in Slave-out |
| MOSI | Output | Master-out Slave-in |
The SPI sends:
- command register (8 bits)
- data in (8 bits)
- status register (8 bits)
- data out (8 bits)
The SPI word length is fixed at 16 bits.
In every SPI word, the command register dictates the functions on the I2C bus, and the data in holds the data to be sent by the I2C bus. Similarly, the last bit of the status register is the acknowledge bit and the data out is the data received over the I2C line in the previous I2C cycle.
At the end of every SPI bus:
- The slave select line goes high; indicating a word complete.
- The master executes an I2C bus as per the value of command register at that time.
After a fixed delay, depending on the frequency of the I2C SCL, another SPI word can be sent. The minimum delay between two SPI words is the I2C SCL clock frequency.