1.3. Implementing the Design
You can implement the design by using the source code and allocating the appropriate signal and control lines to the general purpose I/O (GPIO) lines of the Altera devices. You require an SPI master and an I2C slave as additional resources to demonstrate this implementation.
The MAX II design uses an EPM240 device. You can also implement this application in MAX V and MAX 10 devices.
Note: The MAX II design has been implemented in Verilog and successful operation has been demonstrated using the MDN-B2 demo board. The source code, testbench, and the complete Quartus II project are available in the provided design example files.