Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

Download PDF
ID 683599
Date 10/05/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Low Latency 40G for ASIC Proto Ethernet Intel FPGA IP Design Example User Guide Archive 4. Document Revision History for Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Ethernet Toolkit Overview 2.7. Low Latency 40G for ASIC Proto Ethernet Design Example Registers 2.8. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
2.6. Ethernet Toolkit Overview x
2.6.1. Features
1. Quick Start Guide
2. Design Example Description
3. Low Latency 40G for ASIC Proto Ethernet Intel FPGA IP Design Example User Guide Archive
4. Document Revision History for Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.3
IP Version 19.1.0

The Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the Intel® Quartus® Prime IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

In addition, you can download the compiled hardware design to the Intel device-specific development kit for interoperative testing. The Intel® FPGA IP also includes a compilation-only example project that you can use to quickly estimate IP core area and timing.

The Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP supports design example generation with a wide range of parameters. However, the design examples do not cover all possible parameterizations of the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Core.

Table 1.  List of Supported Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example Variants
Variant Simulation Compilation-Only Project Hardware Design Example
MAC and PCS √ √ √
PCS Only √ √ √
Figure 1. Development Steps for the Design Example
Related Information
Level Two Title