Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

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ID 683599
Date 10/05/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Low Latency 40G for ASIC Proto Ethernet Intel FPGA IP Design Example User Guide Archive 4. Document Revision History for Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Ethernet Toolkit Overview 2.7. Low Latency 40G for ASIC Proto Ethernet Design Example Registers 2.8. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
2.6. Ethernet Toolkit Overview x
2.6.1. Features
1. Quick Start Guide
2. Design Example Description
3. Low Latency 40G for ASIC Proto Ethernet Intel FPGA IP Design Example User Guide Archive
4. Document Revision History for Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

1.1.1. Design Example Parameters

Table 2.  Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings. When you select a design from the Preset library, this field shows the selected design.
Example Design Files

The files to generate for the different development phase.

  • Simulation—generates the necessary files for simulating the example design.
  • Synthesis—generates the synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Edition software for hardware testing and perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an Intel development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is not available, there is no supported board for the options that you select.

None: This option excludes the hardware aspects for the design example.

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