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2. Design Example Description
The 40G Ethernet design example demonstrates the functions of the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP core with integrated MAC and PHY solution compliant with the IEEE 802.3 (2010) standard. You can generate the design from the Example Design tab in the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP parameter editor.
To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench and hardware design example use this variation as the DUT. If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.
Low Latency 40G for ASIC Proto Ethernet IP allows you to implement the IP with or without MAC via Select USER MAC mode parameter selection:
- PCS+MAC—allows you to integrate the MAC within the IP.The IP integrates the MAC.
- PCS_Only—allows you to generate IP without MAC. You need to create a separate user MAC.
Note: The testbench demonstrates a basic test of the IP core. It is not intended to be a substitute for a full verification environment. You must perform more extensive verification of your own Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP design in simulation and in hardware.