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1.1. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP
1.2. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP
1.3. Ethernet Packet Classifier Intel® FPGA IP
1.4. Ethernet Design Example Components v17.0
1.5. Ethernet Design Example Components v16.0
1.6. Ethernet Design Example Components User Guide Archives
1.1.1. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v20.1.1
1.1.2. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v20.0.0
1.1.3. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v19.3.0
1.1.4. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v19.2.0
1.1.5. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v18.0
1.1.6. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v17.1
1.2.1. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.5
1.2.2. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.4
1.2.3. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.0
1.2.4. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v19.2.0
1.2.5. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v18.0
1.2.6. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v17.1
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1.2.2. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.4
Quartus® Prime Version | Description | Impact |
---|---|---|
23.4 | Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP has lower timing margin for Agilex™ 7 I-Series OPNs with device density code of 041. | — |