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3.3.2. Receiver Clocks
The transceiver requires a receiver reference clock, rx_serial_refclk. This clock trains the receiver PLL in the transceiver.
- For SD-SDI operation, the clock must be nominally 1/4th of the serial data rate (for example, 67.5 MHz). The clock does not have to be frequency locked to the data.
- For HD-SDI operation, the clock must be nominally 1/20th of the serial data rate. The clock does not have to be frequency locked to the data, because the design only uses it for the training of the receiver PLL.
- For dual or triple standard operation, the receiver reference clock must be 148.5 MHz. In this mode, the transceiver oversamples the SD-SDI signals by a factor of 11.
All receiver interfaces share a common receiver reference clock.
Video Standard | Clock Frequency (MHz) |
---|---|
SD-SDI | 67.5 |
HD-SDI | 74.175 or 74.25 |
Dual or triple standard | 148.35 or 148.56 |
3G-SDI | 148.35 or 148.5 |
Figure 15. Receiver Clocks for Different Standards
6 For correct SD-SDI operation, you must use only 148.5 MHz