3.2. Receiver
- SD/HD-SDI receiver descrambler and word aligner
- HD-SDI receiver CRC and LN extractor
- Transceiver, plus control, and interface logic with multirate (dual or triple standard) SD/HD-SDI transmitter operation
- Receiver framing, with extraction of video timing signals
- Identification and tracking of ancillary data
- NRZI decoding and descrambling
- Word alignment
- Video timing flags extraction
- RP168 switching compliance
- HD-SDI LN extraction
- HD-SDI CRC
- Accessing transceiver
The received data is NRZI decoded and descrambled and then presented as a word-aligned parallel output—20 bit for HD-SDI; 10 bit for SD-SDI (refer to Table 3–16 on page 3–41 for rxdata bus definition).
rxdata | SD-SDI | HD-SDI | 3G-SDI Level A | 3G-SDI Level B |
---|---|---|---|---|
[19:10] | Unused | Y | Y | Cb, Y, Cr, Y multiplex (link A) |
[9:0] | Cb, Y, Cr, Y multiplex | C | C | Cb, Y, Cr, Y multiplex (link B) |
The receiver interface extracts and tracks the F, V, and H timing signals in the received data. Active picture and ancillary data words are also identified for your use.
For HD-SDI, the received CRC is checked for the luma and chroma channels. The LN is also extracted and provided as an output from the design.
NRZI Decoding and Descrambling
The descrambler module provides the channel decoding function that is common to both SDI and HD-SDI. It implements the NRZI decoding followed by the required descrambling. The algorithm indicated by SMPTE259M figure C.1 is iteratively applied to the receiver data, with the LSB processed first.
Word Alignment
The aligner word aligns the descrambled receiver data such that the bit order of the output data is the same as that of the original video data.
Video Standard | EAV and SAV Sequences |
---|---|
SD-SDI | 3FF 000 000 |
HD-SDI | 3FF 3FF 000 000 000 000 |
3G-SDI Level A | 3FF 3FF 000 000 000 000 |
3G-SDI Level A | 3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000 |
The aligner matches the selected pattern in the descrambled receiver data. If the pattern is detected at any of the possible word alignments, then a flag is raised and the matched alignment is indicated. This process is applied continuously to the receiver data.
The second stage of the aligner determines the correct word alignment for the data. It looks for three consecutive TRSs with the same alignment, and then stores that alignment. If two consecutive TRSs are subsequently detected with a different alignment, then this new alignment is stored.
The final stage of the aligner applies a barrel shift function to the received data to generate the correctly aligned parallel word output. For this SDI MegaCore function, the barrel shifter allows the design to instantly switch from one alignment to another.
Video Timing Flags Extraction
The TRS match module extracts the F, V, and H video timing flags from the received data. You can use these flags for receiver format detection, or in the implementation of a flywheel function.
The TRS match module also identifies the line number and CRC words for HD-SDI.
RP168 Switching Compliance
To meet the RP168 requirements, the transceiver must be able to recover by the end of the switching line.
Standard/ Data Rate | Format | RP168 Support | Switching Source |
---|---|---|---|
Fixed | Switch (same format) | Yes | HD-1080i30 to HD-1080i30 |
Fixed | Switch | No | HD-1080 to HD-720 |
Switch | Fixed | No | HD-1080 to SD-525 |
Switch | Switch | No | HD-1080 to SD-525 |
The following figures show the behaviors of the aligner and format blocks during the RP168 switching.
The format block latches the user input en_sync_switch signal for three lines to realign to a new TRS alignment immediately. During switching, you see zero interrupt at downstream. The trs_locked and frame_locked signals never get deasserted during sync switch.
HD-SDI LN Extraction
The HD-SDI LN extraction module extracts and formats the LN words defined by SMPTE292M section 5.4 from the HD-SDI chroma channel. The design provides the LN as an output.
HD-SDI CRC Checking
The CRC module checks the CRC defined by SMPTE292M section 5.5 for the HD-SDI luma and chroma channels.
The check is implemented by recalculating the CRCs for each received video line and then checking the results against the CRC data received. If the results differ, an error flag is asserted. There are separate error flags for the luma and chroma channels. The flag is held asserted until the next check is performed.
Accessing Transceiver
The Intel® Quartus® Prime Standard Edition software enables you to access the transceiver through the unencrypted ALTGX wrapper file. You can access the ALTGX wrapper files for Arria II GX, Arria V, Cyclone IV GX, and Stratix IV GX configurations.
- Edit the ALTGX wrapper file, using legal range provided in the respective device handbooks.
- Use analog control through the ALTGX_RECONFIG megafunction.
Editing the ALTGX Wrapper File
To change the settings of the parameters, edit the legal ranges in the ALTGX wrapper file.
For example, to change the voltage output differential control setting from 4 to 7, change the following line in the wrapper file:
alt4gxb_component.vod_ctrl_setting = 4
to this line:
alt4gxb_component.vod_ctrl_setting = 7
Using Analog Control
If you want the flexibility to access and control the ALTGX settings, use the ALTGX_RECONFIG megafunction to enable analog reconfiguration. Use the analog control to edit the default settings of the following transceiver parameters:
- Voltage output differential
- Pre-emphasis control pre-tap
- Pre-emphasis control 1st post-tap
- Pre-emphasis control 2nd post-tap
- Equalizer DC gain
- Equalizer DC control
The ALTGX_RECONFIG megafunction connects with ALTGX using reconfig_togxb[3:0] and reconfig_fromgxb[16:0] ports for a single channel.
To enable the analog control and channel reconfiguration during run time, use the reconfig_mode_sel signal.