SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

3.2. Receiver

The receiver contains the following elements:
  • SD/HD-SDI receiver descrambler and word aligner
  • HD-SDI receiver CRC and LN extractor
  • Transceiver, plus control, and interface logic with multirate (dual or triple standard) SD/HD-SDI transmitter operation
  • Receiver framing, with extraction of video timing signals
  • Identification and tracking of ancillary data
The receiver performs the following functions:
  • NRZI decoding and descrambling
  • Word alignment
  • Video timing flags extraction
  • RP168 switching compliance
  • HD-SDI LN extraction
  • HD-SDI CRC
  • Accessing transceiver
Figure 6. SDI Receiver Block DiagramThe figure below shows the top-level block diagram for the SDI receiver.


The received data is NRZI decoded and descrambled and then presented as a word-aligned parallel output—20 bit for HD-SDI; 10 bit for SD-SDI (refer to Table 3–16 on page 3–41 for rxdata bus definition).

Table 8.  Bit Allocation for rxdata for Supported Video StandardsThe table below lists the bit allocation for rxdata.
rxdata SD-SDI HD-SDI 3G-SDI Level A 3G-SDI Level B
[19:10] Unused Y Y Cb, Y, Cr, Y multiplex (link A)
[9:0] Cb, Y, Cr, Y multiplex C C Cb, Y, Cr, Y multiplex (link B)

The receiver interface extracts and tracks the F, V, and H timing signals in the received data. Active picture and ancillary data words are also identified for your use.

For HD-SDI, the received CRC is checked for the luma and chroma channels. The LN is also extracted and provided as an output from the design.

NRZI Decoding and Descrambling

The descrambler module provides the channel decoding function that is common to both SDI and HD-SDI. It implements the NRZI decoding followed by the required descrambling. The algorithm indicated by SMPTE259M figure C.1 is iteratively applied to the receiver data, with the LSB processed first.

Word Alignment

The aligner word aligns the descrambled receiver data such that the bit order of the output data is the same as that of the original video data.

Table 9.  EAV and SAV SequencesThe EAV and SAV sequences determine the correct word alignment. The table below lists the pattern for each standard.
Video Standard EAV and SAV Sequences
SD-SDI 3FF 000 000
HD-SDI 3FF 3FF 000 000 000 000
3G-SDI Level A 3FF 3FF 000 000 000 000
3G-SDI Level A 3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000

The aligner matches the selected pattern in the descrambled receiver data. If the pattern is detected at any of the possible word alignments, then a flag is raised and the matched alignment is indicated. This process is applied continuously to the receiver data.

The second stage of the aligner determines the correct word alignment for the data. It looks for three consecutive TRSs with the same alignment, and then stores that alignment. If two consecutive TRSs are subsequently detected with a different alignment, then this new alignment is stored.

The final stage of the aligner applies a barrel shift function to the received data to generate the correctly aligned parallel word output. For this SDI MegaCore function, the barrel shifter allows the design to instantly switch from one alignment to another.

Video Timing Flags Extraction

The TRS match module extracts the F, V, and H video timing flags from the received data. You can use these flags for receiver format detection, or in the implementation of a flywheel function.

The TRS match module also identifies the line number and CRC words for HD-SDI.

RP168 Switching Compliance

To meet the RP168 requirements, the transceiver must be able to recover by the end of the switching line.

Table 10.  Supported Video Switching TypeThe table below lists the supported video switching type.
Standard/ Data Rate Format RP168 Support Switching Source
Fixed Switch (same format) Yes HD-1080i30 to HD-1080i30
Fixed Switch No HD-1080 to HD-720
Switch Fixed No HD-1080 to SD-525
Switch Switch No HD-1080 to SD-525

The following figures show the behaviors of the aligner and format blocks during the RP168 switching.

Figure 7. Aligner Block BehaviorThe aligner block immediately aligns to the next TRS timing based on the user input en_sync_switch signal.

The format block latches the user input en_sync_switch signal for three lines to realign to a new TRS alignment immediately. During switching, you see zero interrupt at downstream. The trs_locked and frame_locked signals never get deasserted during sync switch.

Figure 8. Format Block Behavior

HD-SDI LN Extraction

The HD-SDI LN extraction module extracts and formats the LN words defined by SMPTE292M section 5.4 from the HD-SDI chroma channel. The design provides the LN as an output.

HD-SDI CRC Checking

The CRC module checks the CRC defined by SMPTE292M section 5.5 for the HD-SDI luma and chroma channels.

Note: This module is common to the receiver and the transmitter.

The check is implemented by recalculating the CRCs for each received video line and then checking the results against the CRC data received. If the results differ, an error flag is asserted. There are separate error flags for the luma and chroma channels. The flag is held asserted until the next check is performed.

Accessing Transceiver

The Intel® Quartus® Prime Standard Edition software enables you to access the transceiver through the unencrypted ALTGX wrapper file. You can access the ALTGX wrapper files for Arria II GX, Arria V, Cyclone IV GX, and Stratix IV GX configurations.

You can use one of the following ways to access the ALTGX wrapper files:
  • Edit the ALTGX wrapper file, using legal range provided in the respective device handbooks.
  • Use analog control through the ALTGX_RECONFIG megafunction.
Note: Do not reinstantiate the customized ALTGX wrapper file using the IP catalog if you do not want to lose the default content of the wrapper file after regeneration.

Editing the ALTGX Wrapper File

To change the settings of the parameters, edit the legal ranges in the ALTGX wrapper file.

For example, to change the voltage output differential control setting from 4 to 7, change the following line in the wrapper file:

alt4gxb_component.vod_ctrl_setting = 4

to this line:

alt4gxb_component.vod_ctrl_setting = 7

Note: To know the exact legal ranges for a specific Intel device, refer to the respective device handbooks.

Using Analog Control

If you want the flexibility to access and control the ALTGX settings, use the ALTGX_RECONFIG megafunction to enable analog reconfiguration. Use the analog control to edit the default settings of the following transceiver parameters:

  • Voltage output differential
  • Pre-emphasis control pre-tap
  • Pre-emphasis control 1st post-tap
  • Pre-emphasis control 2nd post-tap
  • Equalizer DC gain
  • Equalizer DC control

The ALTGX_RECONFIG megafunction connects with ALTGX using reconfig_togxb[3:0] and reconfig_fromgxb[16:0] ports for a single channel.

To enable the analog control and channel reconfiguration during run time, use the reconfig_mode_sel signal.

Transceiver Clock

Figure 9. Receiver Clocking SchemeThe figure below shows the general clocking scheme for the receiver.
Level Two Title