SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

1.3. General Description

The Society of Motion Picture and Television Engineers (SMPTE) defines an SDI standard that video system designers use widely as an interconnect between equipment in video production facilities.

The SDI IP core handles the following SDI data rates:

  • 270 megabits per second (Mbps) SD-SDI, as defined by SMPTE259M-1997 10-Bit 4:2:2 Component Serial Digital Interface
  • 1.5 gigabits per second (Gbps) HD-SDI, as defined by SMPTE292M-1998 Bit-Serial Digital Interface for High Definition Television Systems
  • 3-Gbps SDI, as defined by SMPTE425M-AB 2006 3Gb/s Signal/Data Serial Interface– Source Image Format Mapping
  • Preliminary dual link SDI support, as defined by SMPTE372M-Dual Link 1.5Gb/s Digital Interface for 1920×1080 and 2048×1080 Picture Formats
  • Dual standard support for 270-Mbps and 1.5-Gbps SDI
  • Triple standard support for 270-Mbps, 1.5-Gbps, and 3-Gbps SDI
  • Triple standard support for SD-SDI, HD-SDI, and 3G-SDI
  • SMPTE425M Level A support (direct source image formatting)
  • SMPTE425M Level B support (dual link mapping)
Table 4.  SDI Standard Support

All SDI standards, except SD-SDI, require a transceiver-based device.

Table below lists the SDI standard support for various FPGA devices.
Device Family SDI Standard
SD-SDI HD-SDI 3G-SDI HD-SDI Dual Link3 Dual Standard Triple Standard
Arria II GX Yes Yes Yes Yes Yes Yes
Arria V Yes Yes Yes Yes Yes Yes
Stratix IV 4 Yes Yes Yes Yes Yes Yes
Stratix V 4 Yes Yes Yes Yes Yes Yes
Cyclone IV GX (EP4CGX15, EP4CGX30) Yes — — — — —
Cyclone IV GX (EP4CGX30 (F484), EP4CGX50, EP4CGX75, EP4CGX110, EP4CGX150) Yes Yes Yes Yes Yes Yes
Cyclone V 5 Yes Yes Yes Yes Yes Yes
3 The HD-SDI dual link supports timing difference up to 40 ns between link A and link B, fulfilling the SMPTE372M requirement.
4 Only Stratix IV and Stratix V variants with transceivers support all SDI rates.
5 The 3G-SDI standard is not supported in Cyclone V devices with transceiver speed grade 7, due to the excessive data rate required.
Level Two Title