LVDS SERDES Intel® FPGA IP Release Notes

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ID 683575
Date 4/08/2024
Public
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LVDS SERDES Intel® FPGA IP Release Notes
LVDS SERDES Intel® FPGA IP Release Notes x
LVDS SERDES Intel FPGA IP (intel_lvds) v23.1.0 LVDS SERDES Intel FPGA IP (intel_lvds) v23.0.0 LVDS SERDES Intel FPGA IP v20.0.1 LVDS SERDES Intel FPGA IP v20.0.0 LVDS SERDES Intel FPGA IP v19.5.0 LVDS SERDES Intel FPGA IP v19.4.0 LVDS SERDES Intel FPGA IP v19.3.0 LVDS SERDES Intel® FPGA IP v18.1 LVDS SERDES Intel® FPGA IP v18.0 Intel® FPGA LVDS SERDES IP Core v17.1 Altera LVDS SERDES IP Core v17.0 Altera LVDS SERDES IP Core v14.1 Altera LVDS SERDES IP Core v14.0 Arria 10 Edition
LVDS SERDES Intel® FPGA IP Release Notes

LVDS SERDES Intel FPGA IP (intel_lvds) v23.1.0

Table 1.  v23.1.0 2024.04.01
Quartus® Prime Version Description Impact
24.1 Added support for Agilex™ 5 FPGAs and SoCs. —
Table 2.  v23.1.0 2023.12.04
Quartus® Prime Version Description Impact
23.4

Added the Transmitter Settings tab to support tx_outclock with these parameters:

  • Enable tx_outclock port
  • Desired tx_outclock phase shift (degrees)
  • Actual tx_outclock phase shift (degrees)
  • Tx_outclock division factor
Upgrade and recompilation of the IP are required only if you want to use tx_outclock.
Timing optimizations to make meeting setup and hold requirements easier. Upgrade and recompilation are not required.
Level Two Title