Visible to Intel only — GUID: hco1421698025382
Ixiasoft
LVDS SERDES Intel FPGA IP (intel_lvds) v23.1.0
LVDS SERDES Intel FPGA IP (intel_lvds) v23.0.0
LVDS SERDES Intel FPGA IP v20.0.1
LVDS SERDES Intel FPGA IP v20.0.0
LVDS SERDES Intel FPGA IP v19.5.0
LVDS SERDES Intel FPGA IP v19.4.0
LVDS SERDES Intel FPGA IP v19.3.0
LVDS SERDES Intel® FPGA IP v18.1
LVDS SERDES Intel® FPGA IP v18.0
Intel® FPGA LVDS SERDES IP Core v17.1
Altera LVDS SERDES IP Core v17.0
Altera LVDS SERDES IP Core v14.1
Altera LVDS SERDES IP Core v14.0 Arria 10 Edition
Visible to Intel only — GUID: hco1421698025382
Ixiasoft
Altera LVDS SERDES IP Core v14.0 Arria 10 Edition
| Description | Impact |
|---|---|
| Added feature that creates .sdc file for generated designs (previously only for example designs) | — |
| Added support for external PLL mode | — |
| Added option to clock TX core registers using reference clock | — |