Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 1/31/2025
Public

Visible to Intel only — GUID: pvn1481130024643

Ixiasoft

Document Table of Contents

16.4.2.5.5. Host Data Buffer Alignment

The transmit and receive data buffers in system memory must be aligned to a 32‑bit boundary.