AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

Download PDF
ID 683559
Date 11/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.4. JESD204B Intel® FPGA IP and ADC Configurations

The JESD204B Intel® FPGA IP core parameters in this hardware checkout are natively supported by the AD9208 device. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9208 operating conditions.

The hardware checkout testing implements the JESD204B Intel® FPGA IP core with the following parameter configuration.

Global setting for all configuration:

  • N’ = 16
  • CS = 0
  • CF = 0
  • Subclass = 1
  • FPGA Management Clock (MHz) = 100
  • Character Replacement = Enabled
  • PCS option = Soft PCS
Table 6.  Parameter Configuration
LMF HD S N ADC Sampling Clock (MHz) FPGA Transceiver Reference Clock (MHz) 3 FPGA Link Clock (MHz) 4 FPGA Frame Clock (MHz) 4 Lane Rate (Gbps) DDC Enabled Decimation Factor Data Pattern
112 0 1 14 800 400 400 400 16.0 No 1 PRBS-9 Ramp
114 0 2 14 800 400 400 400 16.0 No 1 PRBS-9 Ramp
211 1 1 14 1600 400 400 400 16.0 No 1 PRBS-9 Ramp
212 0 2 14 1600 400 400 400 16.0 No 1 PRBS-9 Ramp
411 1 2 14 3000 375 375 375 15.0 No 1 PRBS-9 Ramp
412 0 4 14 3000 375 375 375 15.0 No 1 PRBS-9 Ramp
811 1 4 14 3000 187.5 187.5 187.5 7.5 No 1 PRBS-9 Ramp
812 0 8 14 3000 187.5 187.5 187.5 7.5 No 1 PRBS-9 Ramp
124 0 1 14 400 400 400 400 16.0 No 1 PRBS-9 Ramp
128 0 2 14 400 400 400 200 16.0 No 1 PRBS-9 Ramp
222 0 1 14 800 400 400 400 16.0 No 1 PRBS-9 Ramp
224 0 2 14 800 400 400 400 16.0 No 1 PRBS-9 Ramp
421 1 1 14 1600 400 400 400 16.0 No 1 PRBS-9 Ramp
422 0 2 14 1600 400 400 400 16.0 No 1 PRBS-9 Ramp
821 1 2 14 3000 375 375 375 15.0 No 1 PRBS-9 Ramp
822 0 4 14 3000 375 375 375 15.0 No 1 PRBS-9 Ramp
148 0 1 16 400 400 400 200 16.0 Yes 1 PRBS-9 Ramp
244 0 1 16 800 400 400 400 16.0 Yes 2 PRBS-9 Ramp
248 0 2 16 800 400 400 200 16.0 Yes 2 PRBS-9 Ramp
442 0 1 16 1600 400 400 400 16.0 Yes 2 PRBS-9 Ramp
444 0 2 16 1600 400 400 400 16.0 Yes 2 PRBS-9 Ramp
841 1 1 16 3000 375 375 375 15.0 Yes 2 PRBS-9 Ramp
842 0 2 16 3000 375 375 375 15.0 Yes 2 PRBS-9 Ramp
288 0 1 16 400 400 400 200 16.0 Yes 2 PRBS-9 Ramp
484 0 1 16 800 400 400 400 16.0 Yes 2 PRBS-9 Ramp
488 0 2 16 800 400 400 200 16.0 Yes 2 PRBS-9 Ramp
882 0 1 16 1600 400 400 400 16.0 Yes 2 PRBS-9 Ramp
884 0 2 16 1600 400 400 400 16.0 Yes 2 PRBS-9 Ramp
3 The FPGA transceiver reference clock is used to clock the transceiver.
4 The core reference clock from Si5341 with frequency of the FPGA transceiver reference clock is used to derive frame clock and link clock frequencies.
Level Two Title