Other IP Cores Release Notes

ID 683556
Date 5/07/2018
Public
Document Table of Contents

1.68. RAM: 2-Port IP Core v17.1

Table 70.  v17.1 November 2017
Description Impact
Added support for Intel® Stratix® 10 devices.
  • Added ECC Parity Flip feature for memory blocks error correction code support. This feature dynamically flip the parity value generated in the encoder of M20K blocks to observe the ECC behavior through simulation.
  • Added True Dual Ports Dual Clock Emulator feature to emulates a TDP dual clock mode using single clock mode. This feature provides backward compatibility with Intel® Arria® 10 devices.