| ip |
Contains the IP instance files for all the Intel FPGA IP instances in the design:
- A DisplayPort IP (transmitter and receiver)
- A PLL that generates clocks at the top level of the design
- All the IP that make up the Platform Designer system for the processing pipeline.
. |
| master_image |
Contains pre_compiled.sof, which is a precompiled board programming file for the design. |
| non_acds_ip |
Contains source code for additional IP in this design that Intel® Quartus® Prime does not include. |
| sdc |
Contains an SDC file that describes the additional timing constraints that this design requires. The SDC files included automatically with the IP instances do not handle these constraints. |
| software |
Contains source code, libraries, and build scripts for the software that runs on the embedded Nios II processor to control the high-level functionality of the design. |
| udx10_dp |
A folder into which Intel® Quartus® Prime generates output files for the Platform Designer system. The udx10_dp.sopcinfo output file allows you to generate the memory initialization file for the Nios II processor software memory. You need not first generate the full Platform Designer system. |
| non_acds_ip.ipx |
This IPX file declares all of the IP in the non_acds_ip folder to Platform Designer so it appears in the IP Library. |
| README.txt |
Brief instructions to build and run the design. |
| top.qpf |
The Intel® Quartus® Prime project file for the design. |
| top.qsf |
The Intel® Quartus® Prime project settings file for the design. This file lists all the files required to build the design, along with the pin assignments and a number of other project settings. |
| top.v |
The top-level Verilog HDL file for the design. |
| udx10_dp.qsys |
The Platform Designer system that contains the video processing pipeline, the Nios II processor, and its peripherals. |