AN 495: IDE/ATA Controller Using Altera MAX Series

Download PDF
ID 683523
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. IDE/ATA Controller Using Altera MAX Series
1. IDE/ATA Controller Using Altera MAX Series x
1.1. IDE/ATA Controller and Interface 1.2. IDE/ATA Controller Using Supported Altera Devices 1.3. Implementation 1.4. Acknowledgments 1.5. Document Revision History
1.2. IDE/ATA Controller Using Supported Altera Devices x
1.2.1. CPU Interface Block 1.2.2. PIO Controller Block 1.2.3. IDE Interface Block
1. IDE/ATA Controller Using Altera MAX Series

1.3. Implementation

The detailed description of the implementation is based on the MAX II devices. This application can also be implemented in MAX V and MAX 10 devices.

This design example can be implemented using a MAX II device such as the EPM570 device or any other MAX II device with the required general-purpose I/O (GPIO) pin count and LEs.

This design example has been implemented in Verilog and successful operation has been demonstrated using the MDN-B2 demo board, as described in this application note.

Level Two Title