AN 495: IDE/ATA Controller Using Altera MAX Series

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ID 683523
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. IDE/ATA Controller Using Altera MAX Series
1. IDE/ATA Controller Using Altera MAX Series x
1.1. IDE/ATA Controller and Interface 1.2. IDE/ATA Controller Using Supported Altera Devices 1.3. Implementation 1.4. Acknowledgments 1.5. Document Revision History
1.2. IDE/ATA Controller Using Supported Altera Devices x
1.2.1. CPU Interface Block 1.2.2. PIO Controller Block 1.2.3. IDE Interface Block
1. IDE/ATA Controller Using Altera MAX Series

1.2. IDE/ATA Controller Using Supported Altera Devices

The IDE interface supports two modes of data transfer—the PIO mode and the DMA mode. This design example is restricted to mode 0 of PIO data transfer.

Table 1.  Description of Interface SignalsLists the brief description of the various signals as shown in the Basic Block Diagram of an IDE/ATA Interface figure.
Signal Size Direction Description
clk 1 Input Same as the clock of the processor. This example works at a clock frequency of 100 MHz.
arst 1 Input Asynchronous active-low reset to reset the controller.
iderst 1 Input Active-high signal to reset the IDE device.
ideen 1 Input Active-high signal to enable the IDE device.
pioiordyen 1 Input Active-high signal to enable the IORDY signal from the IDE device.
piorqst 1 Input Active-high signal to start a PIO data transfer cycle.
pioaddr[3:0] 4 Input 4-bit bus to select the device address and the chip select signals of the IDE device.
piodatain[15:0] 16 Input 16-bit bus to send the data to the IDE device.
piowe 1 Input

Active-high signal to set the direction of data transfer.

  • piowe is 1—write operation
  • piowe is 0—read operation
intrrqstsignal 1 Output Signal to interrupt the CPU.
pioack 1 Output Signal to indicate the end of a PIO read/write cycle.
piodataout [15:0] 16 Output 16-bit bus to hold the data read from the IDE device.
rstn 1 Output Active-low signal to reset the IDE device.
ddo [15:0] 16 Output 16-bit data bus that transfers the data sent by the CPU to the device. The lower 8 bits are used for 8-bit data transfers.
da [2:0] 3 Output 3-bit active-high signal. Contains the binary coded address asserted by the host to access a register or data port in the device.
cs0n 1 Output

Active-low chip select signals from the host used to select the command block or control block registers.

  • cs0 is 0—select control register
  • cs1 is 0—select command register
  • cs0 or cs1 is 0 or 1—the device ignores transitions on DIOR-/DIOW- and release the data bus.
cs1n 1
diorn 1 Output Active-low strobe signal asserted by the host to read device registers or the data port.
diown 1 Output Active-low strobe signal asserted by the host to write to the device registers or the data port.
dstrb 1 Output data-in strobe signal from the device. The rising edge of dstrb latches the data from the device into the host.
ddi [15:0] 16 Input 16-bit data bus that contains the data read from the IDE device.
iordy 1 Input This signal is negated to extend the host transfer cycle of any host register access (read or write) when the device is not ready to respond to a data transfer request. Optional for mode 0 but required for higher modes.
intrq 1 Input Used by the selected device to notify the host of an event. The device internal interrupt pending state is set when such an event occurs.
ddoe 1 Output Used to read data from the IDE device. The data on the ddi bus is put on the data lines piodataout after the signal is brought low.

Section Content
CPU Interface Block
PIO Controller Block
IDE Interface Block

Level Two Title