FIFO Intel® FPGA IP User Guide

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ID 683522
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. FIFO Intel® FPGA IP User Guide
1. FIFO Intel® FPGA IP User Guide x
1.1. Configuration Methods 1.2. Specifications 1.3. FIFO Functional Timing Requirements 1.4. SCFIFO ALMOST_EMPTY Functional Timing 1.5. FIFO Output Status Flag and Latency 1.6. FIFO Metastability Protection and Related Options 1.7. FIFO Synchronous Clear and Asynchronous Clear Effect 1.8. SCFIFO and DCFIFO Show-Ahead Mode 1.9. Different Input and Output Width 1.10. DCFIFO Timing Constraint Setting 1.11. Coding Example for Manual Instantiation 1.12. Design Example 1.13. Gray-Code Counter Transfer at the Clock Domain Crossing 1.14. Guidelines for Embedded Memory ECC Feature 1.15. FIFO Intel® FPGA IP User Guide Archives 1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
1.2. Specifications x
1.2.1. Verilog HDL Prototype 1.2.2. VHDL Component Declaration 1.2.3. VHDL LIBRARY-USE Declaration 1.2.4. FIFO Signals 1.2.5. FIFO Parameter Settings
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect x
1.7.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
1.10. DCFIFO Timing Constraint Setting x
1.10.1. Embedded Timing Constraint 1.10.2. User Configurable Timing Constraint
1.10.2. User Configurable Timing Constraint x
1.10.2.1. SDC Commands
1. FIFO Intel® FPGA IP User Guide

1.2.4. FIFO Signals

This section provides diagrams of the SCFIFO and DCFIFO blocks of the FIFO Intel® FPGA IP core to help in visualizing their input and output ports. This section also describes each port in detail to help in understanding their usages, functionality, or any restrictions. For better illustrations, some descriptions might refer you to a specific section in this user guide.
Figure 1. SCFIFO and DCFIFO Input and Output Signals

For the SCFIFO block, the read and write signals are synchronized to the same clock; for the DCFIFO block, the read and write signals are synchronized to the rdclk and wrclk clocks respectively. The prefixes wr and rd represent the signals that are synchronized by the wrclk and rdclk clocks respectively.

Table 2.  Input and Output Ports DescriptionThis table lists the signals of the FIFO Intel® FPGA IP core. The term “series” refers to all the device families of a particular device. For example, “ Stratix® series” refers to the Stratix® IV and Stratix® V, unless specified otherwise.
Port Type Required Description
clock 2 Input Yes Positive-edge-triggered clock.
wrclk 3 Input Yes Positive-edge-triggered clock.

Use to synchronize the following ports:

  • data
  • wrreq
  • wrfull
  • wrempty
  • wrusedw
rdclk 3 Input Yes Positive-edge-triggered clock.

Use to synchronize the following ports:

  • q
  • rdreq
  • rdfull
  • rdempty
  • rdusedw
data 4 Input Yes

Holds the data to be written in the FIFO Intel® FPGA IP core when the wrreq signal is asserted. If you manually instantiate the FIFO Intel® FPGA IP core, ensure the port width is equal to the lpm_width parameter.

wrreq 4 Input Yes Assert this signal to request for a write operation.

Ensure that the following conditions are met:

  • Do not assert the wrreq signal when the full (for SCFIFO) or wrfull (for DCFIFO) port is high. Enable the overflow protection circuitry or set the overflow_checking parameter to ON so that the FIFO Intel® FPGA IP core can automatically disable the wrreq signal when it is full.
  • The wrreq signal must meet the functional timing requirement based on the full or wrfull signal.
  • Do not assert the wrreq signal during the deassertion of the aclr signal. Violating this requirement creates a race condition between the falling edge of the aclr signal and the rising edge of the write clock if the wrreq port is set to high. For both the DCFIFO functions that target Stratix® and Cyclone® series, you have the option to automatically add a circuit to synchronize the aclr signal with the wrclk clock, or set the write_aclr_synch parameter to ON. Use this option to ensure that the restriction is obeyed.
rdreq 4 Input Yes Assert this signal to request for a read operation. The rdreq signal acts differently in normal mode and show-ahead mode.

Ensure that the following conditions are met:

  • Do not assert the rdreq signal when the empty (for SCFIFO) or rdempty (for DCFIFO) port is high. Enable the underflow protection circuitry or set the underflow_checking parameter to ON so that the FIFO Intel® FPGA IP core can automatically disable the rdreq signal when it is empty.
  • The rdreq signal must meet the functional timing requirement based on the empty or rdempty signal.
sclr 2

aclr 4

Input No Assert this signal to clear all the output status ports, but the effect on the q output may vary for different FIFO configurations.

There are no minimum number of clock cycles for aclr signals that must remain active.

By default, the aclr port is enabled. Make sure either aclr or sclr port is enabled and included in the design to ensure the correct functionality of the FIFO.

q 4 Output Yes

Shows the data read from the read request operation. For the SCFIFO function and DCFIFO function, the width of the q port must be equal to the width of the data port. If you manually instantiate the FIFO functions, ensure that the port width is equal to the lpm_width parameter.

For the DCFIFO_MIXED_WIDTHS function, the width of the q port can be different from the width of the data port. If you manually instantiate the FIFO function, ensure that the width of the q port is equal to the lpm_width_r parameter. The FIFO function supports a wide write port with a narrow read port, and vice versa. However, the width ratio is restricted by the type of RAM block, and in general, are in the power of 2.

full 2

wrfull 3

rdfull 3

Output No When asserted, the FIFO Intel® FPGA IP core is considered full. Do not perform write request operation when the FIFO Intel® FPGA IP core is full.

In general, the rdfull signal is a delayed version of the wrfull signal. However, for Stratix®  III devices and later, the rdfull signal functions as a combinational output instead of a derived version of the wrfull signal. Therefore, you must always refer to the wrfull port to ensure whether or not a valid write request operation can be performed, regardless of the target device.

empty 2

wrempty 3

rdempty 3

Output No When asserted, the FIFO Intel® FPGA IP core is considered empty. Do not perform read request operation when the FIFO Intel® FPGA IP core is empty.

In general, the wrempty signal is a delayed version of the rdempty signal. However, for Stratix®  III devices and later, t he wrempty signal functions as a combinational output instead of a derived version of the rdempty signal. Therefore, you must always refer to the rdempty port to ensure whether or not a valid read request operation can be performed, regardless of the target device.

almost_full 2 Output No Asserted when the usedw signal is greater than or equal to the almost_full_value parameter. It is used as an early indication of the full signal.
almost_empty 2 Output No Asserted when the usedw signal is less than the almost_empty_value parameter. It is used as an early indication of the empty signal. 5
usedw 2

wrusedw 3

rdusedw 3

Output No Show the number of words stored in the FIFO.

Ensure that the port width is equal to the lpm_widthu parameter if you manually instantiate the SCFIFO function or the DCFIFO function. For the DCFIFO_MIXED_WIDTH function, the width of the wrusedw and rdusedw ports must be equal to the LPM_WIDTHU and lpm_widthu_r parameters respectively.

For Stratix® , Stratix®  GX, and Cyclone® devices, t he FIFO Intel® FPGA IP core shows full even before the number of words stored reaches its maximum value. Therefore, you must always refer to the full or wrfull port for valid write request operation, and the empty or rdempty port for valid read request operation regardless of the target device.
Note: Stored data may not be available for reading. Refer to FIFO Output Status Flag and Latency for "wrreq to empty" and "rdreq to empty" latency to ensure that the data is ready before reading the FIFO.
eccstatus 6 Output No A 2-bit wide error correction status port. Indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit occurs.
  • 00: No error
  • 01: Illegal
  • 10: A correctable error occurred and the error has been corrected at the outputs; however, the memory array has not been updated.
  • 11:An uncorrectable error occurred and uncorrectable data appears at the output.

This port is only available for Arria® 10 devices using M20K memory block type.

The DCFIFO function rdempty output may momentarily glitch when the aclr input is asserted. To prevent an external register from capturing this glitch incorrectly, ensure that one of the following is true:

  • The external register must use the same reset which is connected to the aclr input of the DCFIFO function, or
  • The reset connected to the aclr input of the DCFIFO function must be asserted synchronous to the clock which drives the external register.

The output latency information of the FIFO Intel® FPGA IP core is important, especially for the q output port, because there is no output flag to indicate when the output is valid to be sampled.

2 Only applicable for the SCFIFO function.
3 Applicable for both of the DCFIFO functions.
4 Applicable for the SCFIFO, DCFIFO, and DCFIFO_MIXED_WIDTH functions.
5 Under certain condition, the SCFIFO asserts the empty signal without ever asserting the almost_empty signal. Refer to SCFIFO ALMOST_EMPTY Functional Timing for more details.
6 Not applicable for the DCFIFO_MIXED_WIDTHS function.
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