Intel® Stratix® 10 General Purpose I/O User Guide

Download PDF
ID 683518
Date 9/29/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 I/O Overview 2. Intel® Stratix® 10 I/O Architecture and Features 3. Intel® Stratix® 10 I/O Design Considerations 4. Intel® Stratix® 10 I/O Implementation Guides 5. GPIO Intel® FPGA IP Reference 6. Document Revision History for Intel® Stratix® 10 General Purpose I/O User Guide
1. Intel® Stratix® 10 I/O Overview x
1.1. Intel® Stratix® 10 I/O and Differential I/O Buffers 1.2. Intel® Stratix® 10 I/O Migration Support
2. Intel® Stratix® 10 I/O Architecture and Features x
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices 2.2. I/O Element Structure in Intel® Stratix® 10 Devices 2.3. Programmable IOE Features in Intel® Stratix® 10 Devices 2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices 2.5. External I/O Termination for Intel® Stratix® 10 Devices
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices x
2.1.1. Intel® Stratix® 10 I/O Standards Support 2.1.2. Intel® Stratix® 10 I/O Standards Voltage Support
2.2. I/O Element Structure in Intel® Stratix® 10 Devices x
2.2.1. I/O Bank Architecture in Intel® Stratix® 10 Devices 2.2.2. I/O Buffer and Registers in Intel® Stratix® 10 Devices
2.3. Programmable IOE Features in Intel® Stratix® 10 Devices x
2.3.1. Programmable Output Slew Rate Control 2.3.2. Programmable IOE Delay 2.3.3. Programmable Open-Drain Output 2.3.4. Programmable Bus Hold 2.3.5. Programmable Pull-Up Resistor 2.3.6. Programmable Pre-Emphasis 2.3.7. Programmable Differential Output Voltage 2.3.8. Programmable Current Strength
2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices x
2.4.1. RS OCT without Calibration in Intel® Stratix® 10 Devices 2.4.2. RS OCT with Calibration in Intel® Stratix® 10 Devices 2.4.3. RT OCT with Calibration in Intel® Stratix® 10 Devices 2.4.4. Dynamic OCT 2.4.5. Differential Input RD OCT 2.4.6. OCT Calibration Block in Intel® Stratix® 10 Devices
2.5. External I/O Termination for Intel® Stratix® 10 Devices x
2.5.1. Single-Ended I/O Termination 2.5.2. Differential I/O Termination for Intel® Stratix® 10 Devices
2.5.2. Differential I/O Termination for Intel® Stratix® 10 Devices x
2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 2.5.2.2. LVDS, RSDS, and Mini-LVDS Termination 2.5.2.3. LVPECL Termination
3. Intel® Stratix® 10 I/O Design Considerations x
3.1. Guideline: VREF Sources and VREF Pins 3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards 3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing 3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down 3.6. Guideline: Maximum DC Current Restrictions 3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks 3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400 3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
4. Intel® Stratix® 10 I/O Implementation Guides x
4.1. GPIO Intel® FPGA IP 4.2. Verifying Resource Utilization and Design Performance 4.3. GPIO Intel® FPGA IP Timing 4.4. GPIO Intel® FPGA IP Design Examples 4.5. Verifying Pin Migration Compatibility 4.6. IP Migration to the GPIO IP Core
4.1. GPIO Intel® FPGA IP x
4.1.1. Release Information for GPIO Intel® FPGA IP 4.1.2. GPIO Intel® FPGA IP Data Paths 4.1.3. Register Packing
4.1.2. GPIO Intel® FPGA IP Data Paths x
4.1.2.1. Input Path 4.1.2.2. Output and Output Enable Paths
4.3. GPIO Intel® FPGA IP Timing x
4.3.1. Timing Components 4.3.2. Delay Elements 4.3.3. Timing Analysis 4.3.4. Timing Closure Guidelines
4.3.3. Timing Analysis x
4.3.3.1. Single Data Rate Input Register 4.3.3.2. Full-Rate or Half-Rate DDIO Input Register 4.3.3.3. Single Data Rate Output Register 4.3.3.4. Full-Rate or Half-Rate DDIO Output Register
4.4. GPIO Intel® FPGA IP Design Examples x
4.4.1. GPIO Intel® FPGA IP Synthesizable Intel® Quartus® Prime Design Example 4.4.2. GPIO Intel® FPGA IP Simulation Design Example
4.6. IP Migration to the GPIO IP Core x
4.6.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores 4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
5. GPIO Intel® FPGA IP Reference x
5.1. GPIO Intel® FPGA IP Parameter Settings 5.2. GPIO Intel® FPGA IP Interface Signals
5.2. GPIO Intel® FPGA IP Interface Signals x
5.2.1. Shared Signals 5.2.2. Data Bit-Order for Data Interface 5.2.3. Data Interface Signals and Corresponding Clocks
1. Intel® Stratix® 10 I/O Overview
2. Intel® Stratix® 10 I/O Architecture and Features
3. Intel® Stratix® 10 I/O Design Considerations
4. Intel® Stratix® 10 I/O Implementation Guides
5. GPIO Intel® FPGA IP Reference
6. Document Revision History for Intel® Stratix® 10 General Purpose I/O User Guide

4.3.3. Timing Analysis

The Intel® Quartus® Prime software does not automatically generate the SDC timing constraints for the GPIO IP. You must manually enter the timing constraints.

Follow the timing guidelines and examples to ensure that the Timing Analyzer analyzes the I/O timing correctly.

  • To perform proper timing analysis for the I/O interface paths, specify the system level constraints of the data pins against the system clock pin in the .sdc file.
  • To perform proper timing analysis for the core interface paths, define these clock settings in the .sdc file:
    • Clock to the core registers
    • Clock to the I/O registers for the simple register and DDIO modes

Section Content
Single Data Rate Input Register
Full-Rate or Half-Rate DDIO Input Register
Single Data Rate Output Register
Full-Rate or Half-Rate DDIO Output Register

Related Information
Level Two Title