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2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices
2.2. I/O Element Structure in Intel® Stratix® 10 Devices
2.3. Programmable IOE Features in Intel® Stratix® 10 Devices
2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices
2.5. External I/O Termination for Intel® Stratix® 10 Devices
3.1. Guideline: VREF Sources and VREF Pins
3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing
3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards
3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing
3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down
3.6. Guideline: Maximum DC Current Restrictions
3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks
3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400
3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
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4.3.3.3. Single Data Rate Output Register
Figure 36. Single Data Rate Output Register
Command | Command Example | Description |
---|---|---|
create_clock and create_generated_clock | create_clock -name sdr_out_clk -period "100 MHz" sdr_out_clk create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk |
Generate the source clock and the output clock to transmit. |
set_output_delay | set_output_delay -clock sdr_out_outclk 0.45 sdr_out_data | Instructs the Timing Analyzer to analyze the output data to transmit against the output clock to transmit. |