Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

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Date 10/06/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide
1. Introduction x
1.1. Terms and Acronyms 1.2. MCDMA IP Modes
2. Design Example Detailed Description x
2.1. Design Example Overview 2.2. Hardware and Software Requirements 2.3. PIO using MCDMA Bypass Mode 2.4. Avalon-ST Packet Generate/Check 2.5. Avalon-ST Device-side Packet Loopback 2.6. Avalon-MM DMA 2.7. BAM_BAS Traffic Generator and Checker 2.8. External Descriptor Controller
2.1. Design Example Overview x
2.1.1. H-Tile MCDMA IP - Design Examples for Endpoint 2.1.2. P-Tile MCDMA IP - Design Examples for Endpoint 2.1.3. F-Tile MCDMA IP - Design Examples for Endpoint 2.1.4. R-Tile MCDMA IP - Design Examples for Endpoint
2.3. PIO using MCDMA Bypass Mode x
2.3.1. Avalon-ST PIO using MCDMA Bypass Mode 2.3.2. Avalon-MM PIO using MCDMA Bypass Mode
2.3.1. Avalon-ST PIO using MCDMA Bypass Mode x
2.3.1.1. Single-Port Avalon-ST PIO using MCDMA Bypass Mode
2.3.2. Avalon-MM PIO using MCDMA Bypass Mode x
2.3.2.1. Simulation Results 2.3.2.2. Hardware Test Results
2.4. Avalon-ST Packet Generate/Check x
2.4.1. Single-Port Avalon-ST Packet Generate/Check
2.4.1. Single-Port Avalon-ST Packet Generate/Check x
2.4.1.1. Simulation Waveforms 2.4.1.2. Simulation Log 2.4.1.3. Hardware Test Result
2.5. Avalon-ST Device-side Packet Loopback x
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. Avalon-MM DMA x
2.6.1. Simulation Results 2.6.2. Hardware Test Results
2.7. BAM_BAS Traffic Generator and Checker x
2.7.1. BAM_BAS Traffic Generator and Checker Example Design Register Map
2.8. External Descriptor Controller x
2.8.1. Registers 2.8.2. Hardware Test Results
2.8.1. Registers x
2.8.1.1. GCSR Registers (Base address 64’h00000) 2.8.1.2. QCSR Registers(Base address 64’h10000)
3. Design Example Quick Start Guide x
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Intel® Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Intel® Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Intel® Quartus® Prime x
3.2.1. Procedure
3.3. Simulating the Design Example x
3.3.1. Testbench Overview 3.3.2. Supported Simulators 3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.4. Run the Simulation Script 3.3.5. Steps to Run the Simulation 3.3.6. View the Results
3.3.5. Steps to Run the Simulation x
3.3.5.1. Steps to Run the Simulation : QuestaSim* / Questa* Intel® FPGA Edition 3.3.5.2. Steps to Run the Simulation : VCS* / VCS* MX 3.3.5.3. Steps to Run the Simulation : Xcelium*
3.5. Running the Design Example Application on a Hardware Setup x
3.5.1. Program the FPGA 3.5.2. Quick Start Guide
3.5.2. Quick Start Guide x
3.5.2.1. Software Test Setup 3.5.2.2. Driver Support 3.5.2.3. MCDMA Custom Driver 3.5.2.4. MCDMA DPDK Poll Mode Driver 3.5.2.5. MCDMA Kernel Mode Network Device Driver
3.5.2.3. MCDMA Custom Driver x
3.5.2.3.1. Prerequisites 3.5.2.3.2. Software Setup 3.5.2.3.3. Run the Reference Example Application 3.5.2.3.4. Testing Bitstream Configuration beyond 256 Channels (for MCDMA Custom Driver) 3.5.2.3.5. External Descriptor Mode Verification
3.5.2.3.1. Prerequisites x
3.5.2.3.1.1. Configuration Changes from BIOS 3.5.2.3.1.2. External Packages 3.5.2.3.1.3. Set the Boot Parameters
3.5.2.3.2. Software Setup x
3.5.2.3.2.1. Installing the Linux Kernel Driver 3.5.2.3.2.2. Build and Install User Space Library 3.5.2.3.2.3. Enabling VFs and Create Guest VM by Using QEMU 3.5.2.3.2.4. Establish Communication Between Host and QEMU
3.5.2.3.3. Run the Reference Example Application x
3.5.2.3.3.1. Meta Data Test 3.5.2.3.3.2. Custom PIO Read Write Test 3.5.2.3.3.3. BAM Test 3.5.2.3.3.4. BAS Test 3.5.2.3.3.5. Packet Gen Test
3.5.2.4. MCDMA DPDK Poll Mode Driver x
3.5.2.4.1. Prerequisites 3.5.2.4.2. Install PMD and Test Application (for CentOS) 3.5.2.4.3. Install PMD and Test Application (for Ubuntu) 3.5.2.4.4. Create VM Environment 3.5.2.4.5. Run the Reference Example Application
3.5.2.4.1. Prerequisites x
3.5.2.4.1.1. Set the Boot Parameters 3.5.2.4.1.2. Configuration Changes from BIOS 3.5.2.4.1.3. Install and Build Testpmd
3.5.2.4.4. Create VM Environment x
3.5.2.4.4.1. Enable VFs 3.5.2.4.4.2. Create Guest VM by using QEMU 3.5.2.4.4.3. Establish Communication Between Host and VM
3.5.2.4.5. Run the Reference Example Application x
3.5.2.4.5.1. Channel ID VF PF Verification 3.5.2.4.5.2. Example of Verifying on an AVMM Design 3.5.2.4.5.3. Testing Bitstream Configuration beyond 256 Channels (for DPDK Poll Mode Driver) 3.5.2.4.5.4. BAM Test 3.5.2.4.5.5. BAS Test
3.5.2.5. MCDMA Kernel Mode Network Device Driver x
3.5.2.5.1. Build and Install Netdev Driver 3.5.2.5.2. Enable VFs if SRIOV is Supported 3.5.2.5.3. Configure the Number of Channels Supported on the Device 3.5.2.5.4. Configure the MTU Value 3.5.2.5.5. Configure the Device Communication 3.5.2.5.6. Configure Transmit Queue Selection Mechanism 3.5.2.5.7. Test Procedure by Using Name Space Environment 3.5.2.5.8. PIO Test
3.5.2.5.6. Configure Transmit Queue Selection Mechanism x
3.5.2.5.6.1. MCDMA Queue Selection 3.5.2.5.6.2. Transmit Packet Steering (XPS) 3.5.2.5.6.3. Default
1. Introduction
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide

2.7.1. BAM_BAS Traffic Generator and Checker Example Design Register Map

The Traffic generator and checker control and status registers are byte addresses. The Traffic generator checker register map is mapped to BAR0 in the Example Design..
Table 7.  Read start address (Offset 16’h0000)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31:0] RAdd R/W 0 This register contains the base addresses that the Traffic Checker reads from.
Table 8.  Read count (Offset 16’h0008)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] Mode R/W 0

0: Fixed no of transfers

1: non-stop transfers
[30:12] rsvd     Reserved
[11:0] RCnt R/W 0 Write to the RCnt registers to specify the number of transfers to execute. Reading from one of these registers returns the number of transfers that have occurred since it was last read.
Table 9.  Read error count (Offset 16’h0010)
Bit[63:0] Name R/W Default Description
[63:12] rsvd     Reserved
[11:0] RErr ROC 0 Reading the RErr register returns the number of errors detected since the register was last read. A maximum of one error is counted per clock cycle.
Table 10.  Read control (Offset 16’h0018)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] enable R/W 0 0: stop 1: start
[30:8] rsvd     Reserved
[7:0] transfer_size   0 This register configures the burst length per transfer (ideal value for x16 is 8 & x8 is 16). Zero is not a legal value.
Table 11.  Write start address (Offset 16’h0020)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31:0] WAdd R/W 0 This register contains the base addresses that the Traffic Generator writes to.
Table 12.  Write count (Offset 16’h0028)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] Mode R/W 0

0: Fixed no of transfers

1: non-stop transfers
[30:12] rsvd     Reserved
[11:0] WCnt R/W 0 Write to the WCnt registers to specify the number of transfers to execute. Reading from one of these registers returns the number of transfers that have occurred since it was last read.
Table 13.  Write error count (Offset 16’h0030)
Bit[63:0] Name R/W Default Description
[63:12] rsvd     Reserved
[11:0] WErr ROC 0 Reserved (Write error detection not available yet). Because the write error detection feature is not available yet, you cannot get a valid number of errors by reading the WErr register.
Table 14.  Write control (Offset 16’h0038)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] enable R/W 0 0: stop 1: start
[30:8] rsvd     Reserved
[7:0] transfer_size   0 This register configures the burst length per transfer (ideal value for x16 is 8 & x8 is 16). Zero is not a legal value.
Table 15.  Read address mapping table (Offset 16’h0100)The Read address mapping table is 32 locations and 64bit wide each.
Bit[63:0] Name R/W Default Description
[63:0] raDM R/W 0 This register contains the Traffic Checker address mapping table that maps thirty-two 1 MB regions of the Avalon-MM memory space into thirty-two 1 MB regions of the PCIe address space. The module occupies only 32MB of the Avalon-MM address space, and only needs a 25-bit wide address bus, leaving space for other Avalon-MM slaves.
Table 16.  Write address mapping table (Offset 16’h0200)The Write address mapping table is 32 locations and 64bit wide each.
Bit[63:0] Name R/W Default Description
[63:0] WAdm R/W 0 This register contains the Traffic Generator address mapping table that maps thirty-two 1 MB regions of the Avalon-MM memory space into thirty-two 1 MB regions of the PCIe address space. The module occupies only 32MB of the Avalon-MM address space, and only needs a 25-bit wide address bus, leaving space for other Avalon-MM slaves.
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