Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide

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ID 683510
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview x
1.1. Release Information 1.2. Device Family Support 1.3. Commands and Responses 1.4. Mailbox Client with Avalon® Streaming Interface Intel FPGA IP User Guide Document Archives 1.5. Document Revision History for the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide
1.2. Device Family Support x
1.2.1. Parameters 1.2.2. Interfaces
1.2.2. Interfaces x
1.2.2.1. Clock and Reset Interfaces 1.2.2.2. Command Interface 1.2.2.3. Response Interface 1.2.2.4. Command Status Interface
1.3. Commands and Responses x
1.3.1. Operation Commands 1.3.2. Error Code Responses 1.3.3. Error Code Recovery
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview

1.2.2. Interfaces

The following figure illustrates the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP interfaces:
Figure 3.  Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Interfaces

For more information about Avalon® streaming interface s, refer to the Avalon Interface Specifications.


Section Content
Clock and Reset Interfaces
Command Interface
Response Interface
Command Status Interface

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