Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide

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ID 683510
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview x
1.1. Release Information 1.2. Device Family Support 1.3. Commands and Responses 1.4. Mailbox Client with Avalon® Streaming Interface Intel FPGA IP User Guide Document Archives 1.5. Document Revision History for the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide
1.2. Device Family Support x
1.2.1. Parameters 1.2.2. Interfaces
1.2.2. Interfaces x
1.2.2.1. Clock and Reset Interfaces 1.2.2.2. Command Interface 1.2.2.3. Response Interface 1.2.2.4. Command Status Interface
1.3. Commands and Responses x
1.3.1. Operation Commands 1.3.2. Error Code Responses 1.3.3. Error Code Recovery
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview

1.3. Commands and Responses

The host controller communicates with the SDM using command and response packets via the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP.

The first word of the command and response packets is a header that provides basic information about the command or response.

Figure 7. Command and Response Header Format in Agilex™ 7
Note: The LENGTH field in the command header must match the command length of corresponding command.

The following table describes the fields of the header command.

Table 7.  Command and Response Header Description
Header Bit Description
Reserved [31:28] Reserved.
ID [27:24] The command ID. The response header returns the ID specified in the command header. Refer to Operation Commands for command descriptions.
0 [23] Reserved.
LENGTH [22:12] Number of words of arguments following the header. The IP responds with an error if a wrong number of words of arguments is entered for a given command.

If there is a mismatch between the command length specified in the command header and the number of words sent. The IP raises bit 3 of the Interrupt Status Register (COMMAND_INVALID) and the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP must be reset.

Reserved [11] Reserved. Must be set to 0.
Command Code/Error Code [10:0] Command Code specifies the command. The Error Code indicates whether the command succeeded or failed.

In the command header, these bits represent command code. In the response header, these bits represent error code. If the command succeeds, the Error Code is 0. If the command fails, refer to the error codes defined in the Error Code Responses.


Section Content
Operation Commands
Error Code Responses
Error Code Recovery

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