Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel® FPGA IP User Guide
Serial Flash Mailbox Client Intel® FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel® FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel® FPGA IP User Guide

Programming the Flash Memory with the Configuration Bitstream

  1. Open Programmer and click Add File. Select the generated JIC programming file (.jic) and click Open.
  2. Check the Program/Configure check box for the attached .jic file.
  3. To begin programming the flash memory with the configuration bitstream, click Start.
  4. Configuration is complete when the progress bar reaches 100%. Power cycle the board. The Intel® Stratix® 10 device configures automatically using the Active Serial (AS) configuration scheme.
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