Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel® FPGA IP User Guide
Serial Flash Mailbox Client Intel® FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel® FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel® FPGA IP User Guide

Serial Flash Mailbox Client Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.1
IP Version 19.1.0
The Serial Flash Mailbox Client Intel® FPGA IP provides access to quad serial flash devices (SPI).

For a complete list of supported flash memory devices refer to the Device Configuration - Support Center web page.

The Serial Flash Mailbox Client Intel® FPGA IP core supports:

  • Direct flash access (write and read) through the Avalon® memory-mapped interface interface
  • Control register access for other operations through the control and status register (CSR) interface
  • Up to 4 kilobytes (KB) or 1024 words data transfers for each quad SPI read and write command
  • Opcodes for the following quad SPI operations:
    • Open
    • Close
    • Set chip select
    • Read data from flash
    • Write data to flash
    • Erase sector
    • Read device register
    • Write device register
    • Send device opcode

Refer to the respective flash device datasheet for a complete list of supported operations for a particular device.


Section Content
Serial Flash Mailbox Client IP Modules
Device Family Support
Signals
Register Map
Response Codes
Using the Serial Flash Mailbox Client Intel FPGA IP
Design Example
Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives
Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide

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