Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel® FPGA IP User Guide
Serial Flash Mailbox Client Intel® FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel® FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel® FPGA IP User Guide

Serial Flash Mailbox Client IP Modules

The following block diagram shows the modules that comprise the Serial Flash Mailbox Client IP.
Figure 1. Serial Flash Mailbox Client IP Modules

You set up quad SPI commands by writing to the CSR. The Serial Flash Mailbox Client IP sends commands to the secure device manager (SDM) in the Intel® Stratix® 10 device. The SDM controls the quad SPI device.

For write commands you prestore the write data in the write data FIFO. For read commands, you read data from the read data FIFO. The write and read data FIFOs store up to 1024 words. The write and read data FIFOs are Avalon® memory-mapped interface slaves. The Serial Flash Mailbox Client IP asserts tine irq signal if the command results in an error response.

Important:

When used as a configuration device or a data storage device with FPGA, do not reset the quad SPI flash. Resetting the quad SPI flash during the FPGA configuration and reconfiguration, or during the read/write/erase operations, causes undefined behavior for quad SPI and the FPGA. To recover, you must power cycle the device.

To reset the quad SPI flash using the external host, you must first complete the FPGA configuration and reconfiguration, or a quad SPI operation, and only then toggle the reset. The quad SPI operation is complete when the IP issues the CLOSE command to close the exclusive access to the quad SPI flash.

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