Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel® FPGA IP User Guide
Serial Flash Mailbox Client Intel® FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel® FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel® FPGA IP User Guide

Prerequisites

You can create a very simple Intel® Quartus® Prime Pro Edition Platform Designer design example to exercise the Serial Flash Mailbox Client Intel® FPGA IP. This design example must meet the following hardware and software requirements:

  • You should be running the Intel® Quartus® Prime Pro Edition software version 18.0 or later.
  • Your Platform Designer design example should include the components in the following figure:
    Figure 6. Required Communication and Host Components for the Serial Flash Mailbox Client Intel® FPGA IP Design Example
    • Instantiate the JTAG to Avalon® Master as host.
    • Instantiate the Serial Flash Mailbox Client Intel® FPGA IP.
    • Connect the Serial Flash Mailbox Client Intel® FPGA IP to JTAG to Avalon® Master Bridge.
    • Set base addresses for csr, rd_mem, and wr_mem.
  • You should be using the Intel® Stratix® 10 SoC Development Kit.
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