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Serial Flash Mailbox Client IP Modules
Device Family Support
Signals
Register Map
Response Codes
Using the Serial Flash Mailbox Client Intel® FPGA IP
Design Example
Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives
Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Prerequisites
Generating the Configuration Bitstream
Programming the Flash Memory with the Configuration Bitstream
Reading the Flash Memory Device Status Register
Reading the Flash Memory Device ID
Reading the Flash Memory Device ID Using the Control Command
Erasing Flash Memory
Reading Flash Memory
Writing Flash Memory
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Erasing Flash Memory
Here are the steps to erase flash memory:
# Write Offset 4 to request access to the flash memory device.
master_write_32 $m $AsmiOpen 0x1
# Write Offset 3 to select the 1st flash memory device attached to the IP.
master_write_32 $m $AsmiChipSelect 0x0
# Write Offset 6 to perform write enable operation to the device.
master_write_32 $m $AsmiWrEnable 0x1
# Writing the address argument to Offset 9 (Perform Sector Erase on address 0x03FF0000)
master_write_32 $m $AsmiSectorErase 0x03FF0000
# Write Offset 5 to close access to the flash memory device.
master_write_32 $m $AsmiClose 0x1