AN 855: PCI Express* High Performance Reference Design for Intel® Cyclone® 10 GX

Download PDF
ID 683504
Date 6/08/2018
Public
Document Table of Contents
Document Table of Contents x
1. PCI Express High Performance Reference Design
1. PCI Express High Performance Reference Design x
1.1. Understanding Throughput in PCI Express 1.2. Deliverables Included with the Reference Design 1.3. Reference Design Functional Description 1.4. Hardware Requirements 1.5. Software Requirements 1.6. Software Installation 1.7. Hardware Installation 1.8. Running the Software Application 1.9. Additional Chaining DMA Commands 1.10. Using SignalTap II 1.11. Performance Benchmarking Results 1.12. Document Revision History
1.1. Understanding Throughput in PCI Express x
1.1.1. Protocol Overhead 1.1.2. Throughput for Posted Writes 1.1.3. Throughput for Reads
1.3. Reference Design Functional Description x
1.3.1. Project Hierarchy
1.7. Hardware Installation x
1.7.1. Programming using the .sof File
1. PCI Express High Performance Reference Design

1.4. Hardware Requirements

The reference design requires the following hardware:
  • The Intel® Cyclone® 10 GX FPGA Development Kit.
  • A computer running Windows driver with an x4/x1 PCI Express slot for the Intel® Cyclone® 10 GX FPGA development board. The software application and hardware are installed on this computer, referred to as computer #1 in this document.
  • A computer with the Intel® Quartus® Prime software for downloading FPGA programming files to the Intel® Cyclone® 10 GX FPGA development board. This computer is referred to as computer #2 in this document.
  • A USB cable or other Intel download cable.
  • A PCI Express x4 to x1 lane converter for x1 operation.
Note: Intel provides x4 and x1 design examples for this reference design. If the PCI Express slot on your motherboard has one lane but you want to use the x4 design example, you must use a lane converter to transfer data from the higher lanes to the lower available lane.
Level Two Title