Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

Download PDF
ID 683500
Date 1/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Intel® Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Intel® Stratix® 10 and Intel® Arria® 10 IP Variants B. Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. Datasheet x
1.1. Intel® Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Intel® Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Intel® Stratix® 10 10GBASE-KR PHY IP Core
5. Intel® Stratix® 10 10GBASE-KR PHY Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals x
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example x
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide x
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Intel® Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description x
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Intel® Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools x
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview x
8.1.1. Features
1. Datasheet
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Intel® Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Intel® Stratix® 10 and Intel® Arria® 10 IP Variants
B. Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

6.5. Transceiver Reconfiguration Signals

You access the transceiver control and status registers using the transceiver reconfiguration interface. This is an Avalon® -MM interface.

The Avalon® -MM interface implements a standard memory-mapped protocol. You can connect an Avalon master to this bus to access the registers of the embedded Transceiver PHY IP core.

Table 17.  Reconfiguration Interface Ports with Shared Native PHY Reconfiguration InterfaceThese signals are synchronous to mgmt_clk.
Signal Name Direction Description
reconfig_write Input Write enable signal. Signal is active high.
reconfig_read Input Read enable signal. Signal is active high.
reconfig_address[10:0] Input Address bus. The lower 10 bits specify address and the upper bit specifies the channel (bit [10] is always 0) .
reconfig_writedata[31:0] Input A 32-bit data write bus. reconfig_address specifies the address.
reconfig_readdata[31:0] Output A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted.
reconfig_waitrequest Output Indicates the Avalon® -MM interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted.
Related Information
Level Two Title