AN 797: Partially Reconfiguring a Design: on Intel® Arria® 10 GX FPGA Development Board

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ID 683497
Date 12/11/2020
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration Controller IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 9: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board

Step 3: Allocating Placement and Routing Region for a PR Partition

For every base revision you create, the PR design flow uses your PR partition region allocation to place the corresponding persona core in the reserved region. To locate and assign the PR region in the device floorplan for your base revision:

  1. Right-click the u_blinking_led instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region.
  2. To view the Logic Lock in the Chip Planner floorplan, right-click the Region Name, and then click Locate Node > Locate in Chip Planner.
  3. To define the properties of the Logic Lock region, click Assignments > Logic Lock Regions Window.
  4. Specify the placement region co-ordinates in the Origin column. The origin corresponds to the lower-left corner of the region. For example, to set a placement region with (X1 Y1) co-ordinates as (69 10), specify the Origin as X69_Y10. The Intel® Quartus® Prime software automatically calculates the (X2 Y2) co-ordinates (top-right) for the placement region from the height and width you specify.
    Note: This tutorial uses the (X1 Y1) co-ordinates - (69 10), and a height and width of 20 for the placement region. You can define any value for the placement region, as long as the region covers the blinking_led logic.
    Figure 5.  blinking_led in Chip Planner
  5. Enable the Reserved and Core-Only options.
  6. Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.
  7. Select Fixed with expansion for the Routing type and click OK. Selecting this option automatically assigns an expansion length of 1.
    Note: The routing region must be larger than the placement region, to provide extra flexibility for the Fitter when the engine routes different personas.
    Figure 6.  Logic Lock Regions Window
Verify that the blinking_led.qsf contains the following assignments, corresponding to your floorplanning: 
set_instance_assignment -name PLACE_REGION "X69 Y10 X88 Y29" -to u_blinking_led
set_instance_assignment -name RESERVE_PLACE_REGION ON -to u_blinking_led
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to u_blinking_led
set_instance_assignment -name ROUTE_REGION "X68 Y9 X89 Y30" -to u_blinking_led
Level Two Title