AN 899: Reducing Compile Time with Fast Preservation

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ID 683493
Date 11/06/2019
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Document Table of Contents
Document Table of Contents x
1. AN 899: Reducing Compile Time with Fast Preservation
1. AN 899: Reducing Compile Time with Fast Preservation x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Module 1: Analyze the Non-Partitioned Design 1.4. Module 2: Preserve Timing-Closed Design Partitions 1.5. Module 3: Optimize with Fast Preservation 1.6. AN 899: Reducing Compile Time with Fast Preservation Revision History
1.3. Module 1: Analyze the Non-Partitioned Design x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: View Design Assistant Results
1.4. Module 2: Preserve Timing-Closed Design Partitions x
1.4.1. Step 1: Create Design Partitions 1.4.2. Step 2: Floorplan the Design Partitions 1.4.3. Step 3: Preserve the Timing-Closed Root Partition
1.5. Module 3: Optimize with Fast Preservation x
1.5.1. Step 1: Create a Project Revision 1.5.2. Step 2: Enable Fast Preservation 1.5.3. Step 3: Import the Root Partition 1.5.4. Step 4: Optimize the Reserved Core Partitions 1.5.5. Step 5: View Fast Preservation Results
1. AN 899: Reducing Compile Time with Fast Preservation

1.4.2. Step 2: Floorplan the Design Partitions

You must define a core-only, reserved, fixed routing region to reserve core resources in the project for the reserved core partition. Ensure that the exclusive placement region size is large enough to contain all core logic in the reserved core partition. Follow these steps to define a core-only, reserved, fixed routing region to reserve core resources in for non-periphery development:
  1. In the Design Partitions Window, right-click the blinking_led_8s instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region.
    Figure 14. Create Logic Lock Region
  2. To modify the region properties, click Assignments > Logic Lock Regions Window.
  3. In the Origin column, specify X165_Y113.
  4. Change the Width to 14, and the Height to 34.
  5. Enable the Reserved and Core-Only options.
  6. Click the Routing Region cell. The Logic Lock Routing Region Settings dialog box appears.
  7. Specify Fixed with expansion with Expansion Length of 1 for the Routing Type. The actual size and location are arbitrary for this tutorial. However, you can view and adjust the Logic Lock Region shape in the Chip Planner.
  8. Repeat steps 1 through 7 to define the following Logic Lock region for the blinking_led_16s instance:
    Figure 15.  Logic Lock Regions
    • Origin—X165_Y149
    • Width—14
    • Height—34
    • Reserved—On
    • Core Only—On
    • Expansion Length—Fixed with expansion 1

    This floorplanning ensures that the ref_clock_in meets timing because the placement location is not too far from output pins.

    Figure 16.  Logic Lock Region Placement
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