AN 899: Reducing Compile Time with Fast Preservation

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ID 683493
Date 11/06/2019
Public
Document Table of Contents
Document Table of Contents x
1. AN 899: Reducing Compile Time with Fast Preservation
1. AN 899: Reducing Compile Time with Fast Preservation x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Module 1: Analyze the Non-Partitioned Design 1.4. Module 2: Preserve Timing-Closed Design Partitions 1.5. Module 3: Optimize with Fast Preservation 1.6. AN 899: Reducing Compile Time with Fast Preservation Revision History
1.3. Module 1: Analyze the Non-Partitioned Design x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: View Design Assistant Results
1.4. Module 2: Preserve Timing-Closed Design Partitions x
1.4.1. Step 1: Create Design Partitions 1.4.2. Step 2: Floorplan the Design Partitions 1.4.3. Step 3: Preserve the Timing-Closed Root Partition
1.5. Module 3: Optimize with Fast Preservation x
1.5.1. Step 1: Create a Project Revision 1.5.2. Step 2: Enable Fast Preservation 1.5.3. Step 3: Import the Root Partition 1.5.4. Step 4: Optimize the Reserved Core Partitions 1.5.5. Step 5: View Fast Preservation Results
1. AN 899: Reducing Compile Time with Fast Preservation

1.2. Downloading Tutorial Design Files

  1. Download and extract the tutorial design files at:
    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an899_fast_preservation_tutorial_files_193.zip
  2. View the extracted tutorial design file directory structure.
Figure 2. Tutorial Directory Structure
Table 1.  Tutorial Design Files
File Name Description
top.sv

Top-level file that instantiates iopll, big_partition1_top, blinking_led_2s, blinking_led_4s, blinking_led_8s, and blinking_led_16s. Also includes logic to drive LED[4:7] as a single, shifting bit.

top.qpf Intel® Quartus® Prime project file that stores project name and revisions.
top.qsf Intel® Quartus® Prime settings file containing project assignments and settings.
big_partition1_top.v Design file that instantiates 20 instances of an OpenCores* design.
blinking_led_2s.sv Logic to drive LED[0] every two seconds.
blinking_led_4s.sv Logic to drive LED[1] every four seconds.
blinking_led_8s.sv Logic to drive LED[2] every eight seconds.
blinking_led_16s.sv Logic to drive LED[3] every 16 seconds.
blinking_led.sdc A Synopsys Design Constraints file that defines the 50 MHz input reference clock.
iopll.ip The IOPLL Intel® FPGA IP instantiated in top. The IP uses a 50 MHz reference clock frequency, and generates 100 MHz and 550 MHz clocks.
tx_dcfifo.ip The dual clock FIFO Intel® FPGA IP instantiated in blinking_led_2s, blinking_led_4s, blinking_led_8s, and blinking_led_16s instances. Has a write clock of 550 MHz and read clock of 100 MHz.
report_timing.tcl A tcl script with Timing Analyzer commands to generate summary of paths reports with least positive or worst slack in each partition, and commands to report timing for two nodes in the partitions that meet timing.
Level Two Title