Visible to Intel only — GUID: beg1554498091697
Ixiasoft
Visible to Intel only — GUID: beg1554498091697
Ixiasoft
1.2. Quad SPI Flash Byte-Addressing
The following table specifies the byte-addressing compatibility of Intel® FPGAs for supported flash memory devices:
FPGA Devices | Required Flash Memory Byte Addressing |
---|---|
Intel® Cyclone® 10 LP devices | 3-byte addressing |
Intel® Arria® 10 Devices | 4-byte addressing |
Arria V, Cyclone V, Stratix® V series Devices |
|
Cyclone IV, Cyclone II, Cyclone III, Arria GX, Arria II, Stratix II, Stratix III, Stratix IV, Stratix IV Devices | 3-byte addressing |
Adding Dummy Clock Cycles
Flash memory devices must read either a 24-bit (3-byte) address, or 32-bit (4-byte) address before the flash device can start receiving data to write to the flash memory, or before outputting the data after the flash memory device receives a read command. Therefore, you must specify (or select a flash memory template that specifies) an appropriate dummy clock cycle value for the flash memory device, as Defining a New Flash Memory Configuration Device describes.