ALTIOBUF IP Core User Guide

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ID 683471
Date 1/13/2020
Public
Document Table of Contents
Document Table of Contents x
ALTIOBUF IP Core User Guide
ALTIOBUF IP Core User Guide x
Device Family Support ALTIOBUF Features I/O Buffer and Dynamic Delay Integration ALTIOBUF Common Application ALTIOBUF Parameters ALTIOBUF Functional Description ALTIOBUF References ALTIOBUF IP Core User Guide Archives Document Revision History for the ALTIOBUF IP Core User Guide
ALTIOBUF Parameters x
Using the Port and Parameter Definitions
ALTIOBUF Functional Description x
ALTIOBUF Input, Output, and OE Paths
ALTIOBUF Input, Output, and OE Paths x
ALTIOBUF Input Buffer ALTIOBUF Output Buffer ALTIOBUF Bidirectional Buffer Dynamic Delay Chain Valid Values Assignments Necessary For Dynamic Delay Chain Usage
ALTIOBUF Input Buffer x
Differential Mode Pin Naming Convention
ALTIOBUF References x
ALTIOBUF Signals and Parameters: As Input Buffer ALTIOBUF Signals and Parameters: As Output Buffer ALTIOBUF Signals and Parameters: As Bidirectional Buffer Verilog HDL Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration
ALTIOBUF IP Core User Guide

ALTIOBUF Signals and Parameters: As Input Buffer

Table 6.   ALTIOBUF (As Input Buffer) Input Ports This table lists the input ports for the ALTIOBUF IP core (as input buffer).
Name Required Description
datain[] Yes The input buffer normal data input port.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The input signal to the I/O output buffer element. For differential signals, this port acquires the positive signal input.

datain_b[] No The negative signal input of a differential signal to the I/O input buffer element. Input port [NUMBER_OF_CHANNELS - 1..0] wide. When connected, the datain_b port is always fed by a pad/port atom. This port is used only if the USE_DIFFERENTIAL_MODE parameter value is TRUE.
io_config_datain No Input port that feeds the datain port of IO_CONFIG for user-driven dynamic delay chain.

Input port used to feed input data to the serial load shift register. The value is a 1-bit wire shared among all I/O instances. This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN parameter value is TRUE.

io_config_clk No Input clock port that feeds the IO_CONFIG for user-driven dynamic delay chain. Input port used as the clock signal of shift register block.

The maximum frequency for this clock is 30 MHz.

The value is a 1-bit wire shared among all I/O instances. This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN parameter value is TRUE.

io_config_clkena[] No Input clock-enable that feeds the ena port of IO_CONFIG for user-driven dynamic delay chain.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. Input port used as the clock enable signal of the shift register block. This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN parameter value is TRUE.

io_config_update No Input port that feeds the IO_CONFIG update port for user-driven dynamic delay chain.

When asserted, the serial load shift register bits feed the parallel load register. The value is a 1-bit wire shared among all I/O instances. This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN parameter value is TRUE.

dynamicterminationcontrol[] No Input signal for bidirectional I/Os.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. When specified, this port selects from the core either Rs code, when the input value is LOW; or Rt code, when the input value is HIGH. Enable Rt only when the bidirectional I/O is receiving input. When the bidirectional I/O is not receiving input, disable this port for optimal output performance and power dissipation.

Value Rs Code Rt Code
0 1 0
1 0 1
Table 7.   ALTIOBUF (As Input Buffer) Output PortsThis table shows the output ports for the ALTIOBUF IP core (as input buffer).
Name Required Description
dataout[] Yes Input buffer output port.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The I/O input buffer element output.

Table 8.   ALTIOBUF (As Input Buffer) ParametersThis table lists the parameters for the ALTIOBUF IP core (as input buffer).
Name Required Type Description
ENABLE_BUS_HOLD No String Specifies whether the bus hold circuitry is enabled. Values are TRUE and FALSE. When set to TRUE, bus hold circuitry is enabled and the previous value, instead of high impedance, is assigned to the output port when there is no valid input. If omitted, the default is FALSE.

Currently, ENABLE_BUS_HOLD and USE_DIFFERENTIAL_MODE cannot be used simultaneously.

USE_DIFFERENTIAL_MODE No String Specifies whether the input buffer is differential. Values are TRUE and FALSE. When set to TRUE, the output is the difference between the datain and datain_b ports. If omitted, the default is FALSE.

Currently, ENABLE_BUS_HOLD and USE_DIFFERENTIAL_MODE cannot be used simultaneously.

USE_IN_DYNAMIC_DELAY_CHAIN No String Specifies whether the input buffer incorporates the user-driven dynamic delay chain in the IP core, specifically, IO_CONFIG and an input delay cell. Values are TRUE and FALSE. If omitted, the default is FALSE.
NUMBER_OF_CHANNELS Yes Integer Specifies the number of I/O buffers that must be instantiated. Value must be greater than or equal to 1. A value of 1 indicates that the buffer is a 1-bit port and accommodates wires; a value greater than 1 indicates that the port can be connected to a bus of width NUMBER_OF_CHANNELS.
USE_DYNAMIC_TERMINATION_CONTROL No String Specifies dynamic termination control. Values are True and False. If omitted, the default is False.
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