2.12.2.24. Status for TX PLDs

E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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ID 683468

Date 8/30/2022

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2.12.2.24. Status for TX PLDs

Offset: 0x351

Status for TX PLDs Fields

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Bit	Name	Description	Access	Reset
24	`err_tx_avst_fifo_overflow`	TX AVST FIFO Overflow Indicates that the FIFO was written while full Overflow would never happen—if it does, this indicates a problem with the way `i_valid` is being driven Once asserted this bit holds value until the `i_clear_internal_error` port is asserted to clear it This bit doesn't need to be polled—`o_internal_err` is asserted if this signal goes high.	`RO`	`0x0`
23	`err_tx_avst_fifo_empty`	TX AVST FIFO ran empty unexpectedly Asserts when the TX FIFO runs empty (regardless of read enable) Does not apply when in MAC Mode Empty should never happen—if it does, this indicates a problem with the way `i_valid` is being driven	`RO`	`0x1`
22	`err_tx_avst_fifo_underflow`	TX AVST FIFO Underflow Indicates that the FIFO was read when empty after steady state reading was established Underflow should never happen—if it does, this indicates a problem with the way `i_valid` is being driven Once asserted this bit holds value until the `i_clear_internal_error` port is asserted to clear it, or the TX datapath is reset This bit doesn't need to be polled—`o_internal_err` is asserted if this signal goes high.	`RO`	`0x0`
21:16	`tx_dsk_active_chans`	Active Channels. [n]=1: Corresponding channel is part of the deskew set and has received a deskew marker since reset This is a sticky bit that clears on reset and `dsk_clear` Use this set of status bits to confirm that channels are receiving deskew markers Remember that single lane channels only uses this when PTP is active, and in that case, uses bits 0 and 4 only Note: This status is for TX EMIB deskew, and has nothing to do with RX skew from the serial line.	`RO`	`0x0`
13:8	`tx_dsk_monitor_err`	Skew Monitor Error Detected [n]=1: An out-of-alignment EMIB deskew marker was detected on EMIB channel n after deskew In single lane mode, channels 0 and 4 are used when PTP is active, where channel 4 is the PTP channel Valid only when `tx_dsk_eval_done` = 1 . Note: This status is for TX EMIB deskew, and has nothing to do with RX skew from the serial line.	`RO`	`0x0`
3:1	`tx_dsk_status`	EMIB Deskew Status 0: 0 cycles of delay added to remove TX EMIB skew 1: 1 cycle of delay added to remove TX EMIB skew 2: 2 cycles of delay added to remove TX EMIB skew 3: 3 cycles of delay added to remove TX EMIB skew 4: 4 cycles of delay added to remove TX EMIB skew 5: 5 cycles of delay added to remove TX EMIB skew 6: Reserved 7: Deskew Error—too much EMIB skew was detected Valid only when `tx_dsk_eval_done` = 1 When an error is detected, `deskew_clear` can be used to restart the deskew state machine Note: This status is for TX EMIB deskew, and has nothing to do with RX skew from the serial line.	`RO`	`0x0`
0	`tx_dsk_eval_done`	Deskew evaluation is complete 1: The TX PLD has finished attempting to deskew the EMIB channels connected to EHIP 0: TX PLD is still waiting for enough TX deskew markers to evaluate deskew Note: Evaluation complete does not mean that deskew was successful; it just means that the deskew state machine has come to a conclusion. This signal is always required for `hip_ready` for multilane channels unless EMIB channels are deliberately excluded from deskew For single lane channels, this signal is only needed when using PTP Note: This deskew is has nothing to do with RX PCS deskew or the serial input.	`RO`	`0x0`