2.11.5. FlexE and OTN Mode TX Interface

E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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Date 8/30/2022

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2.11.5. FlexE and OTN Mode TX Interface

The E-Tile Hard IP for Ethernet Intel FPGA IP TX client interface in FlexE and OTN variations employs the PCS66 interface protocol.

The FlexE and OTN variations allow the application to write 66b blocks to the TX PCS, bypassing the TX MAC.

In FlexE mode, the TX encoder in the PCS is also bypassed.
In OTN mode, both the TX encoder and the scrambler are bypassed.

The client acts as a source and the TX PCS acts as a sink in the transmit direction.

Note: The E-Tile Hard IP for Ethernet Intel FPGA IP provides support for the OTN feature. For further inquiries, contact your nearest Intel sales representative.

Table 36. Signals of the PCS66 TX InterfaceAll interface signals are clocked by the TX clock. The signal names are standard Avalon® streaming interface signals with slight differences to indicate the variations. For example:

For variants with single 10GE/25GE channel: `i_sl_tx_pcs66_d`

For variants with more than 1 channel: `i_sl_tx_pcs66_d[ch-1:0]`

For variants with single 100GE channel: `i_tx_pcs66_d`
Signal Name	Width	Description
`i_sl_tx_pcs66_d` `i_sl_tx_pcs66_d[ch-1:0]` `i_tx_pcs66_d`	66 bits for each channel (10G/25G) 264 bits (100G)	TX PCS 66b data for 1 block. In FlexE mode, the data presented is scrambled. In OTN mode, the data goes directly to the RS-FEC or PMA.
`i_sl_tx_pcs66_valid` `i_sl_tx_pcs66_valid[ch-1:0]` `i_tx_pcs66_valid`	1 bit for each channel	When asserted, indicates that the TX PCS 66b data is valid. Must be asserted when the TX PCS 66b ready signal is asserted.
`o_sl_tx_pcs66_ready` `o_sl_tx_pcs66_ready[ch-1:0]` `o_tx_pcs66_ready`	1 bit for each channel	TX PCS 66b ready signal. When asserted, indicates the PCS is ready to receive new data.
`i_sl_tx_pcs66_am` `i_sl_tx_pcs66_am[ch-1:0]` `i_tx_pcs66_am`	1 bit for each channel	Alignment marker insertion bit. In FlexE and OTN modes, asserting this signal causes the PCS to allow gaps for the alignment markers in place of the data presented on the TX PCS data signal. The application marks the block as an alignment marker and the scrambler does not process the data.

Figure 46. Transmitting Data Using the PCS66 TX InterfaceThe figure shows how to write the 66b blocks directly to the TX PCS in FlexE and OTN mode using the PCS66 TX Interface.

TX data is written as 66b blocks. The blocks are expected to be 66b encoded, with the sync header bits in the rightmost bit positions (bits 1 and 0).

In FlexE mode, the PCS scrambles and stripes the blocks for transmission.
In OTN mode, the PCS only stripes the blocks for transmission. The input data is expected to be already scrambled.

i_tx_pcs66_valid should conform to these conditions:

Assert the valid signal only when the ready signal is asserted, and deassert only when the ready signal is deasserted.
The two signals can be spaced by a fixed latency between 1 and 10 cycles.
When the valid signal deasserts, i_tx_pcs66_d must be paused.

The block order for the PCS66 mode TX interface is the same as the TX PCS interface. Blocks are transmitted from right to left; the first block to be transmitted from the interface is i_tx_pcs66_d[65:0].

The bit order for the PCS66 mode TX interface is the same as the TX PCS interface. Bits are transmitted from right to left; the first bit to be transmitted from the interface is i_tx_pcs66_d[0].

Figure 47. Inserting Alignment Markers

When PCS66 TX interface is used for FlexE mode, the timing of alignment marker insertion can be controlled from the fabric. The same operations can be performed on *_sl* versions of the ports, with slight variance:

For 100G channels, the signal causes the alignment markers to be inserted.
For 10G/25G channels, the signal causes the cycle to be treated as invalid for PCS processing (no changes to scramble).

In FlexE mode, the timing of alignment marker insertion is very rigid. Alignment markers cannot be delayed without disrupting the Ethernet link. Use valid cycles to count the alignment markers. When i_tx_pcs66_valid is low, the alignment marker counters and input must freeze.

The number of cycles for i_tx_pcs66_am to remain high for a 100G link is 5 cycles.
The number of cycles for am period for a 100G link is typically 315 in simulation and 81915 in hardware.

OTN streams are expected to include their own alignment markers. In OTN mode with FEC, you must assert i_tx_pcs66_am to indicate the position of the alignment markers. In OTN mode without FEC, i_tx_pcs66_am is optional and you can tie the signal low.

Table 37. Alignment Markers Insertion for PCS Direct, FlexE, and OTN Modes
Mode	AM Insertion Bit	AM Date Insertion	TX Data on AM Cycles	Scrambler	64b/66b Encoding/Decoding
PCS Direct	User-driven	Done by PCS	Ignored	Enabled	Enabled
FlexE	User-driven	Done by PCS	Ignored	Enabled	Disabled
OTN	User-driven	Done by user	AM data	Bypassed	Disabled

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E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

2.11.5. FlexE and OTN Mode TX Interface