E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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ID 683468
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP User Guide 2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core 3. About the E-Tile CPRI PHY Intel® FPGA IP 4. Supported Tools 5. E-tile Hard IP User Guide Archives
2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Supported Features 2.2. E-Tile Hard IP for Ethernet Intel FPGA IP Overview 2.3. IP Core Device Family and Speed Grade Support 2.4. IP Core Verification 2.5. Resource Utilization 2.6. Release Information 2.7. Getting Started 2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters 2.9. Functional Description 2.10. Reset 2.11. Interfaces and Signals 2.12. Register Descriptions 2.13. Document Revision History for the E-tile Hard IP for Ethernet Intel FPGA IP Core
2.3. IP Core Device Family and Speed Grade Support x
2.3.1. E-Tile Hard IP for Ethernet Intel FPGA IP Device Family Support 2.3.2. E-Tile Hard IP for Ethernet Intel FPGA IP Device Speed Grade Support
2.4. IP Core Verification x
2.4.1. Simulation Environment 2.4.2. Compilation Checking 2.4.3. Hardware Testing
2.7. Getting Started x
2.7.1. Installing and Licensing Intel® FPGA IP Cores 2.7.2. Specifying the IP Core Parameters and Options 2.7.3. Generated File Structure 2.7.4. Integrating Your IP Core in Your Design 2.7.5. IP Core Testbenches 2.7.6. Compiling the Full Design
2.7.1. Installing and Licensing Intel® FPGA IP Cores x
2.7.1.1. Intel® FPGA IP Evaluation Mode
2.7.4. Integrating Your IP Core in Your Design x
2.7.4.1. Channel Placement 2.7.4.2. Pin Assignments 2.7.4.3. Clock Requirements 2.7.4.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.4.5. SDC for Multiple E-Tile Instances
2.7.4.1. Channel Placement x
2.7.4.1.1. Guidelines and Restrictions for 24-bonded Channels Variant 2.7.4.1.2. Guidelines and Restrictions for 16-bonded Channels Variant
2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters x
2.8.1. Parameter Editor Parameters 2.8.2. RTL Parameters
2.9. Functional Description x
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC 2.9.2. 1588 Precision Time Protocol Interfaces 2.9.3. PCS, OTN, FlexE, and Custom PCS Modes 2.9.4. Auto-Negotiation and Link Training 2.9.5. TX and RX RS-FEC 2.9.6. PMA Direct Mode 2.9.7. Dynamic Reconfiguration 2.9.8. Ethernet Adaptation Flow for 10G/25G and 100G/4x25G Dynamic Reconfiguration Design Example 2.9.9. Ethernet Adaptation Flow with PTP or with External AIB Clocking 2.9.10. Ethernet Adaptation Flow with Non-external AIB Clocking
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC x
2.9.1.1. MAC TX Datapath 2.9.1.2. MAC RX Datapath 2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 2.9.1.4. Pause Control and Generation Interface 2.9.1.5. Pause Control Frame Filtering 2.9.1.6. Link Fault Signaling 2.9.1.7. Order of Ethernet Transmission
2.9.1.1. MAC TX Datapath x
2.9.1.1.1. TX Preamble, Start, and SFD Insertion 2.9.1.1.2. Source Address Insertion 2.9.1.1.3. Length/Type Field Processing 2.9.1.1.4. Frame Padding 2.9.1.1.5. Frame Check Sequence (CRC-32) Insertion 2.9.1.1.6. Inter-Packet Gap Generation and Insertion
2.9.1.2. MAC RX Datapath x
2.9.1.2.1. RX Preamble Processing 2.9.1.2.2. RX Strict SFD Checking 2.9.1.2.3. RX FCS Checking 2.9.1.2.4. RX Malformed Packet Handling 2.9.1.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 2.9.1.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 2.9.1.2.7. Inter-Packet Gap
2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
2.9.1.3.1. Conditions Triggering XOFF Frame Transmission 2.9.1.3.2. Conditions Triggering XON Frame Transmission
2.9.1.6. Link Fault Signaling x
2.9.1.6.1. Determining Link Fault Condition
2.9.2. 1588 Precision Time Protocol Interfaces x
2.9.2.1. Implementing a 1588 System That Includes a E-Tile Hard IP for Ethernet Intel FPGA IP 2.9.2.2. PTP Timestamp Accuracy 2.9.2.3. PTP Transmit Functionality 2.9.2.4. PTP Receive Functionality 2.9.2.5. External Time-of-Day Module for 1588 PTP Variations 2.9.2.6. PTP Timestamp and TOD Formats 2.9.2.7. 10G/25G TX and RX Unit Interval Adjustment 2.9.2.8. 10G/25G TX and RX PTP Extra Latency 2.9.2.9. 100G PTP TX User Flow 2.9.2.10. 100G PTP RX User Flow 2.9.2.11. 100G RX Virtual Lane Offset Calculation for No FEC Variants 2.9.2.12. 100G UI Adjustment 2.9.2.13. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 2.9.2.14. PTP System Considerations 2.9.2.15. Logic Lock Regions Requirements for PTP Accuracy Advanced Mode
2.9.3. PCS, OTN, FlexE, and Custom PCS Modes x
2.9.3.1. PCS Only Mode 2.9.3.2. OTN Mode 2.9.3.3. FlexE Mode 2.9.3.4. Custom PCS Mode
2.10. Reset x
2.10.1. Reset Sequence
2.10.1. Reset Sequence x
2.10.1.1. Reset Sequence with External AIB Clocking
2.11. Interfaces and Signals x
2.11.1. TX MAC Interface to User Logic 2.11.2. RX MAC Interface to User Logic 2.11.3. TX PCS Interface to User Logic 2.11.4. RX PCS Interface to User Logic 2.11.5. FlexE and OTN Mode TX Interface 2.11.6. FlexE and OTN Mode RX Interface 2.11.7. TX Custom PCS Interface to User Logic 2.11.8. RX Custom PCS Interface to User Logic 2.11.9. PMA Direct Interface 2.11.10. Custom Rate Interface 2.11.11. Deterministic Latency Interface 2.11.12. 1588 PTP Interface 2.11.13. Ethernet Link and Transceiver Signals 2.11.14. Reconfiguration Interfaces and Signals 2.11.15. Miscellaneous Status and Debug Signals 2.11.16. Reset Signals 2.11.17. Clocks
2.11.14. Reconfiguration Interfaces and Signals x
2.11.14.1. Ethernet Reconfiguration Interfaces 2.11.14.2. Transceiver Reconfiguration Interfaces 2.11.14.3. RS-FEC Reconfiguration Interfaces 2.11.14.4. PTP Reconfiguration Interfaces
2.11.17. Clocks x
2.11.17.1. Asynchronous Adapter Clock in 10G/25G Mode 2.11.17.2. Asynchronous Adapter Clock in 100G Mode 2.11.17.3. Clock Network Use Cases
2.11.17.3. Clock Network Use Cases x
2.11.17.3.1. Single 25G Ethernet Channel (with FEC) 2.11.17.3.2. Single 10G Ethernet Channel (without FEC) 2.11.17.3.3. Four 25G Ethernet Channels (with FEC) within a Single FEC Block 2.11.17.3.4. Ethernet 25G x 4 (FEC Off) 2.11.17.3.5. 10G/25G Ethernet Channel with Basic PTP Accuracy Mode 2.11.17.3.6. 10G/25G Ethernet Channel with Advanced PTP Accuracy Mode 2.11.17.3.7. 100G Ethernet with Aggregated FEC 2.11.17.3.8. 100G Ethernet with PTP 2.11.17.3.9. Single 25G Synchronous Ethernet Channel 2.11.17.3.10. Multiple 25G Synchronous Ethernet Channels
2.12. Register Descriptions x
2.12.1. Auto Negotiation and Link Training Registers 2.12.2. PHY Registers 2.12.3. TX MAC Registers 2.12.4. RX MAC Registers 2.12.5. Pause and Priority- Based Flow Control Registers 2.12.6. TX Statistics Counter Registers 2.12.7. RX Statistics Counter Registers 2.12.8. 1588 PTP Registers 2.12.9. RS-FEC Registers 2.12.10. PMA Registers
2.12.1. Auto Negotiation and Link Training Registers x
2.12.1.1. ANLT Sequencer Config 2.12.1.2. ANLT Sequencer Status 2.12.1.3. Auto Negotiation Config Register 1 2.12.1.4. Auto Negotiation Config Register 2 2.12.1.5. Auto Negotiation Status Register 2.12.1.6. Auto Negotiation Config Register 3 2.12.1.7. Auto Negotiation Config Register 4 2.12.1.8. Auto Negotiation Config Register 5 2.12.1.9. Auto Negotiation Config Register 6 2.12.1.10. Auto Negotiation Status Register 1 2.12.1.11. Auto Negotiation Status Register 2 2.12.1.12. Auto Negotiation Status Register 3 2.12.1.13. Auto Negotiation Status Register 4 2.12.1.14. Auto Negotiation Status Register 5 2.12.1.15. AN Channel Override 2.12.1.16. Consortium Next Page Override 2.12.1.17. Consortium Next Page Link Partner Status 2.12.1.18. Link Training Config Register 1 2.12.1.19. Link Training Status Register 1 2.12.1.20. Link Training Config Register for Lane 0 2.12.1.21. Link Training Config Register for Lane 1 2.12.1.22. Link Training Config Register for Lane 2 2.12.1.23. Link Training Config Register for Lane 3
2.12.2. PHY Registers x
2.12.2.1. PHY Module Revision ID 2.12.2.2. PHY Scratch Register 2.12.2.3. Loopback Mode 2.12.2.4. PHY Configuration 2.12.2.5. Reset Sequencer RS-FEC Disable 2.12.2.6. RX CDR PLL Locked 2.12.2.7. TX Datapath Ready 2.12.2.8. Frame Errors Detected 2.12.2.9. Clear Frame Errors 2.12.2.10. RX PCS Status for AN/LT 2.12.2.11. PCS Error Injection 2.12.2.12. Alignment Marker Lock 2.12.2.13. Change in RX PCS Deskew Status 2.12.2.14. BER Count 2.12.2.15. Transfer Ready (AIB reset) Status for EHIP, ELANE, and PTP Channels 2.12.2.16. EHIP, ELANE, and RS-FEC Reset Status 2.12.2.17. PCS Virtual Lane 0 2.12.2.18. PCS Virtual Lane 1 2.12.2.19. PCS Virtual Lane 2 2.12.2.20. PCS Virtual Lane 3 2.12.2.21. Recovered Clock Frequency in KHz 2.12.2.22. TX Clock Frequency in KHz 2.12.2.23. Configuration Fields for TX PLD 2.12.2.24. Status for TX PLDs 2.12.2.25. Status for Dynamic Deskew Buffer 2.12.2.26. Configuration for RX PLD Block 2.12.2.27. Configuration for RX PCS 2.12.2.28. BIP Counter 0 2.12.2.29. BIP Counter 1 2.12.2.30. BIP Counter 2 2.12.2.31. BIP Counter 3 2.12.2.32. BIP Counter 4 2.12.2.33. BIP Counter 5 2.12.2.34. BIP Counter 6 2.12.2.35. BIP Counter 7 2.12.2.36. BIP Counter 8 2.12.2.37. BIP Counter 9 2.12.2.38. BIP Counter 10 2.12.2.39. BIP Counter 11 2.12.2.40. BIP Counter 12 2.12.2.41. BIP Counter 13 2.12.2.42. BIP Counter 14 2.12.2.43. BIP Counter 15 2.12.2.44. BIP Counter 16 2.12.2.45. BIP Counter 17 2.12.2.46. BIP Counter 18 2.12.2.47. BIP Counter 19 2.12.2.48. Timer Window for Hi-BER Checks 2.12.2.49. Hi-BER Frame Errors 2.12.2.50. Error Block Count 2.12.2.51. Deskew Depth 0 2.12.2.52. Deskew Depth 1 2.12.2.53. Deskew Depth 2 2.12.2.54. Deskew Depth 3 2.12.2.55. RX PCS Test Error Count
2.12.3. TX MAC Registers x
2.12.3.1. TX MAC Module Revision ID 2.12.3.2. TX MAC Scratch Register 2.12.3.3. Link Fault Configuration 2.12.3.4. IPG Words to remove per Alignment Marker Period 2.12.3.5. Maximum TX Frame Size 2.12.3.6. TX MAC Configuration 2.12.3.7. EHIP TX MAC Feature Configuration 2.12.3.8. TX MAC Source Address Lower Bytes 2.12.3.9. TX MAC Source Address Higher Bytes
2.12.4. RX MAC Registers x
2.12.4.1. RX MAC Module Revision ID 2.12.4.2. RX MAC Scratch Register 2.12.4.3. Maximum RX Frame Size 2.12.4.4. RX CRC Forwarding 2.12.4.5. Link Fault Status 2.12.4.6. RX MAC Configuration 2.12.4.7. EHIP RX MAC Feature Configuration
2.12.5. Pause and Priority- Based Flow Control Registers x
2.12.5.1. TXSFC Module Revision ID 2.12.5.2. TX SFC Scratch Register 2.12.5.3. Enable TX Pause Ports 2.12.5.4. TX Pause Request 2.12.5.5. Enable Automatic TX Pause Retransmission 2.12.5.6. Retransmit Holdoff Quanta 2.12.5.7. Retransmit Pause Quanta 2.12.5.8. Enable TX XOFF 2.12.5.9. Enable Uniform Holdoff 2.12.5.10. Set Uniform Holdoff 2.12.5.11. Lower 4 bytes of the Destination address for Flow Control 2.12.5.12. Higher 2 bytes of the Destination address for Flow Control 2.12.5.13. Lower 4 bytes of the Source address for Flow Control frames 2.12.5.14. Higher 2 bytes of the Source address for Flow Control frames 2.12.5.15. TX Flow Control Feature Configuration 2.12.5.16. Pause Quanta 0 2.12.5.17. Pause Quanta 1 2.12.5.18. Pause Quanta 2 2.12.5.19. Pause Quanta 3 2.12.5.20. Pause Quanta 4 2.12.5.21. Pause Quanta 5 2.12.5.22. Pause Quanta 6 2.12.5.23. Pause Quanta 7 2.12.5.24. PFC Holdoff Quanta 0 2.12.5.25. PFC Holdoff Quanta 1 2.12.5.26. PFC Holdoff Quanta 2 2.12.5.27. PFC Holdoff Quanta 3 2.12.5.28. PFC Holdoff Quanta 4 2.12.5.29. PFC Holdoff Quanta 5 2.12.5.30. PFC Holdoff Quanta 6 2.12.5.31. PFC Holdoff Quanta 7 2.12.5.32. RXSFC Module Revision ID 2.12.5.33. RXSFC Scratch Register 2.12.5.34. Enable RX Pause Frame Processing 2.12.5.35. Forward Flow Control Frames 2.12.5.36. Lower 4 bytes of the Destination address for RX Pause Frames 2.12.5.37. Higher 2 bytes of the Destination address for RX Pause Frames 2.12.5.38. RX Flow Control Feature Configuration
2.12.6. TX Statistics Counter Registers x
2.12.6.1. TX Statistics Registers
2.12.7. RX Statistics Counter Registers x
2.12.7.1. RX Statistics Registers
3. About the E-Tile CPRI PHY Intel® FPGA IP x
3.1. Supported Features 3.2. E-Tile CPRI PHY Intel® FPGA IP Overview 3.3. E-Tile CPRI PHY Device Family Support 3.4. Resource Utilization 3.5. Release Information 3.6. E-Tile CPRI PHY Intel FPGA IP Core Device Speed Grade Support 3.7. Getting Started 3.8. Parameter Settings 3.9. Functional Description 3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals 3.11. Registers 3.12. Document Revision History for the E-tile CPRI PHY Intel FPGA IP
3.7. Getting Started x
3.7.1. Installing and Licensing Intel® FPGA IP Cores 3.7.2. Specifying the IP Core Parameters and Options 3.7.3. Generated File Structure 3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement 3.7.5. IP Core Testbenches 3.7.6. Compiling the Full Design
3.7.1. Installing and Licensing Intel® FPGA IP Cores x
3.7.1.1. Intel® FPGA IP Evaluation Mode
3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement x
3.7.4.1. One 24.33024 Gbps channel with RS-FEC 3.7.4.2. Two 24.33024 Gbps Channel with RS-FEC 3.7.4.3. Three 24.33024 Gbps channels with RS-FEC 3.7.4.4. Four 24.33024 Gbps channels with RS-FEC 3.7.4.5. Restrictions
3.9. Functional Description x
3.9.1. CPRI PHY Functional Blocks 3.9.2. Dynamic Reconfiguration
3.9.1. CPRI PHY Functional Blocks x
3.9.1.1. E-tile Native PHY 3.9.1.2. Soft Reset Sequencer 3.9.1.3. Latency Measurement
3.9.1.3. Latency Measurement x
3.9.1.3.1. Deterministic Latency Calculation
3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals x
3.10.1. Clock Signals 3.10.2. TX MII Interface 3.10.3. RX MII Interface 3.10.4. TX 8B/10B Interface 3.10.5. RX 8B/10B Interface 3.10.6. Status Interface for 64B/66B Line Rate 3.10.7. Status Interface for 8B/10B Line Rate 3.10.8. Serial I/O Pins 3.10.9. Reconfiguration Interfaces (Avalon-MM)
3.10.9. Reconfiguration Interfaces (Avalon-MM) x
3.10.9.1. CPRI PHY Reconfiguration Interface 3.10.9.2. Transceiver Reconfiguration Interface 3.10.9.3. RS-FEC Reconfiguration Interface
3.11. Registers x
3.11.1. PHY Registers 3.11.2. CPRI PHY Registers 3.11.3. PMA Registers 3.11.4. RS-FEC Registers
3.11.3. PMA Registers x
3.11.3.1. Minimizing PMA Adaptation Time
4. Supported Tools x
4.1. E-Tile Channel Placement Tool 4.2. Ethernet Toolkit Overview 4.3. Document Revision History for the E-tile Channel Placement Tool and the Ethernet Link Inspector
4.2. Ethernet Toolkit Overview x
4.2.1. Features
1. About E-tile Hard IP User Guide
2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core
3. About the E-Tile CPRI PHY Intel® FPGA IP
4. Supported Tools
5. E-tile Hard IP User Guide Archives

2.8.1. Parameter Editor Parameters

The E-Tile Hard IP for Ethernet Intel FPGA IP parameter editor provides the parameters you can set to configure your E-Tile Hard IP for Ethernet Intel FPGA IP variation and simulation and hardware design examples.

The E-Tile Hard IP for Ethernet Intel FPGA IP parameter has three tabs, an IP tab, 10GE/25GE and/or 100GE Tab, and an Example Design tab. For information about the Example Design tab, refer to the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example User Guide.

Table 15.   E-Tile Hard IP for Ethernet Intel FPGA IP Parameters: IP TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.

Parameter

Range

Default Setting

Parameter Description

Core Options
Select Core Variant
  • Single 10GE/25GE
  • 1 to 4 10GE/25GE with optional RSFEC
  • Single 100GE with optional RSFEC
  • 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP
  • Custom PCS with optional RSFEC
 Single 10GE/25GE Select a variant of the E-tile Ethernet core with the types of channels required.

If you choose the 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP variant, you can select to use a 100GE channel or 1 to 4 10GE/25GE channels with or without RS-FEC and/or IEEE 1588 timestamps. These options are switchable at compile time or run time.

Number of Channels of 10GE/25GE
  • Single Channel
  • 2 Channels
  • 3 Channels
  • 4 Channels
 Single Channel Set the number of channels when you select variants that allow 1 to 4 channels.

Resources such as RS-FEC and PTP are more efficient if shared. If your design requires multiple 10GE/25GE channels, consider increasing the number of channels in the core to share resources more efficiently.

Active Channel(s) at startup
  • 10GE/25GE Channel(s)
  • 100GE Channel
 10GE/25GE Channel(s) If you choose the 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP, select the channel (100GE or 10GE/25GE) to be connected to the transceivers at start-up.
Enable IEEE 1588 PTP
  • On
  • Off
 Off Turn on this parameter to add IEEE 1588 PTP Timestamp offload functions to the core. The core can generate 1-step or 2-step TX timestamps and RX timestamps.

This option supports 10/25G and 100G with RS-FEC(528,514) variants.

Note: For 10/25G variants, user transmitted PTP packets must be more than 32 bytes, or else it may break the functionality of the IP core.
Note: 25G with PTP supports only single channel variants if you enable auto-negotiation and link training feature.
Note: Timestamps require some soft logic. To enable the soft logic. Connect the core to a PTP Time-of-Day module that produces TOD values using the 96b IEEE 1588v2 time format.
Note: When PTP is enabled, the external AIB clocking is inherently enabled. The Enable external AIB clocking option is not available when this parameter is turned on.
IEEE1588/PTP channel placement restriction
  • EHIP0/2
  • EHIP1/3
 EHIP0/2 Selects the Ethernet Hard IP core to be used when PTP is enabled. This selection determines the PTP channel placement within an E-tile transceiver:
  • EHIP0/2 uses PTP channel 4,5,16, and 17
  • EHIP1/3 uses PTP channel 6,7,18, and 19
Enable SyncE
  • On
  • Off
 Off Turn on this parameter to enable Synchronous Ethernet (SyncE) operation. This parameter is only available for 10G and 25G variant4.
Note: This parameter is not available when Enable IEEE 1588 PTP is turned on.
Enable RS-FEC
  • On
  • Off
 Off Turn on this parameter to include additional hard logic to perform Reed-Solomon Forward Error Correction (RS-FEC).
Note: 25G with RS-FEC supports only single channel variants when you enable auto-negotiation and link training feature unless Enable external AIB clocking is enabled. This feature is not supported for 10G variants.
First RSFEC Lane
  • first_lane0
  • first_lane1
  • first_lane2
  • first_lane3
 first_lane0 Selects the first RS-FEC lane to be used. There are four lanes in the RS-FEC block. When the RS-FEC block is in fractured mode, any of the four lanes may be selected as the first lane. For multiple channel Native PHY IP core instances with the RS-FEC block enabled, the RS-FEC lanes used must be contiguous and must fit within a single four-channel RS-FEC block.
RSFEC Clocking Mode
  • fec_dir_adp_clk_0
  • fec_dir_adp_clk_1
  • fec_dir_adp_clk_2
  • fec_dir_adp_clk_3
 fec_dir_adp_clk_0 Sets the clocking mode for the RS-FEC block. For RS-FEC with PTP enabled topologies, the clock selection is fixed. In all other cases, this control selects the TX adapter clock used to clock the RS-FEC block.
Enable AN/LT
  • On
  • Off
 Off

Turn on this parameter to enable the IP core to support auto-negotiation as defined in IEEE Standard 802.3-2015 Clause 73 and the 25G/50G Ethernet Consortium Schedule Draft 1-6, and link training as defined in IEEE Standard 802.3-2015 Clauses 92 and 93 and the 25G/50G Ethernet Consortium Schedule Draft 1-6.

Note: Multi-channel 25GE with RS-FEC with Enable AN/LT is supported only if Enable external AIB clocking is enabled.

To use AN in loopback mode, set the Ignore Nonce Field to 1 (Auto Negotiation Config Register 1, offset 0xC0, bit [7]), which disables the Nonce bit checking.

Enable external AIB clocking
  • On
  • Off
 Off Turn on this parameter to enable additional i_clk_aib and i_clk_aib_2x signals to allow external clock sources to drive the datapath in the EHIP core and the EMIB block.

Enables this option for the multi-channel 25G with RS-FEC when Enable AN/LT is set.

Important: When you enable this parameter in multi channels 25G variants, triggering a reset to the master channel's EMIB interface impacts the slave channels operation.
Note: This parameter is not available when Enable IEEE 1588 PTP is turned on.
Enable Multi Profile for DR
  • None
  • 25GE to CPRI
  • 25GE to 1GE
 None This parameter is not supported in Intel® Quartus® Prime Pro Edition software version 21.4.

PTP Options

PTP Accuracy Mode

  • Basic Mode
  • Advanced Mode

Basic Mode

 When selected, specifies the PTP accuracy for selected Ethernet variant.
In 10G/25G Ethernet variant:
  • Basic Mode: PTP accuracy is ± 3 ns
  • Advanced Mode: PTP accuracy is ±1.5 ns
In 100G Ethernet variant:
  • Basic Mode: PTP accuracy is ± 8 ns
  • Advanced Mode: PTP accuracy is not supported.

AN/LT Options

Auto-Negotiation

Enable Auto-Negotiation on Reset

  • On
  • Off

On

If this parameter is turned on, the IP core is configured after reset to implement auto-negotiation as defined in Clause 73 of IEEE Std 802.3–2015. If this parameter is turned off, the IP core does not perform the auto-negotiation after reset. Instead, the auto-negotiation can be re-enabled by control and status register (CSR) setting.

Link Fail Inhibit Time

100–4000 ms

504 ms

Specifies the time before link status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link status is set to OK. For more information, refer to Clause 73 Auto-Negotiation for Backplane Ethernet in IEEE Standard 802.3–2015.

The IP core asserts the o_rx_pcs_ready signal to indicate link status is OK.

In simulation, the default value is 504 corresponds to 1.6 ms.

In hardware, the default value for variants with RS-FEC(544,514) is set to 3 seconds.

Advertise CR Technology Ability
  • On
  • Off
 On

If this parameter is turned on, the IP core advertises CR capability by default. If this parameter is turned off, but auto-negotiation is turned on, the IP core advertises KR capability by default.

Request RSFEC
  • On
  • Off
 On Turn on this parameter to request RS-FEC from remote link partner during auto-negotiation.

This parameter must be turned on when Enable RSFEC is on in order to use KR functionality.

Enable Dynamic RSFEC for KR
  • On
  • Off
 Off
When selected, IP enables the ability to switch from RS-FEC Enabled Mode to RS-FEC Disabled Mode.
Note: Only available if Enable RSFEC is selected. In 25G variants, First RSFEC Lane must be set to first_lane0.
Auto-Negotiation Master
  • Lane 0
  • Lane 1
  • Lane 2
  • Lane 3

Lane 0

Selects the master channel for auto-negotiation.

The IP core allows you to change the master channel dynamically by configuring the CSR setting. Available in 100G modes.

In 100G PAM4 mode, the valid selections are Lane0 and Lane2.

Advertise both 10G and 25G during AN
  • On
  • Off
 Off Turn on this parameter to advertise 10 and 25 Gbps data rate during auto-negotiation. When this parameter is turned off, the IP core advertises only the data rate specified in the Select Ethernet Rate parameter in the 10GE/25GE tab.

This parameter is not available with Single 100GE with optional RSFEC variant or when 100GE Channel is selected as Active Channel(s) at startup.

This feature is not compatible with the PTP, RS-FEC, or external AIB clocking.

Advertise Pause ability

  • On
  • Off

On

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.

Advertise Pause ASM_DIR ability

  • On
  • Off

On

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.

Link Training: General

Enable Link Training on Reset
  • On
  • Off

On

If this parameter is turned on, the IP core is configured after reset to perform link training, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER). LT is defined in Clause 92 of IEEE Std 802.3–2015.

Configuration, Debug and Extension Options
Enable Native PHY Debug Master Endpoint
  • On
  • Off
 On If this parameter is turned on, the Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint that connects internally to the Avalon® memory-mapped slave interface for dynamic reconfiguration. The Native PHY Debug Master Endpoint can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console.
Enable JTAG to Avalon Master Bridge
  • On
  • Off
 Off Turn on this parameter to enable an internal JTAG connection to the Avalon® memory-mapped Master Bridge for register reconfigurations. This connection allows the System Console to run the Ethernet Link Inspector.
Table 16.   E-Tile Hard IP for Ethernet Intel FPGA IP Parameters: 10GE/25GE TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.

Parameter

Range

Default Setting

Parameter Description

General Options 10GE/25GE
Select Ethernet Rate
  • 10G
  • 25G

25G

Selects the IP core Ethernet data rate.
Select Ethernet IP Layers
When Enable RSFEC and Enable IEEE 1588 PTP are off:
  • MAC+PCS
  • PCS Only
  • OTN
  • FlexE
 MAC+PCS

Selects the Ethernet Protocol layers provided by the channel.

Note: RS-FEC is not supported in the 10G data rate.
When Enable RSFEC is ON and Enable IEEE 1588 PTP is OFF:
  • MAC+PCS+RS-FEC
  • PCS+RS-FEC
  • OTN+RS-FEC
  • FlexE+RS-FEC
 MAC+PCS+RS-FEC
When Enable RSFEC and Enable IEEE 1588 PTP are on:
  • MAC+PTP+PCS+RS-FEC
 MAC+PTP+PCS+RSFEC
Include alternate ports
  • On
  • Off
 Off This is an advanced option for applications that need to change the active Ethernet IP layers at run-time. When you turn on this option, all possible datapath interfaces are included in the core, and the active interface depends on the control and status register (CSR) setting.

MAC Options: Basic 10GE/25GE

Note: In PCS Only, OTN, and FlexE variations, these parameters have no effect.
TX Maximum Frame Size 65–65535 1518 Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters.

In variations without MAC, this parameter has no effect and remains at the default value of 1518.

RX Maximum Frame Size 65–65535 1518 Maximum packet size (in bytes) the IP core can receive on the Ethernet link without reporting an oversized packet in the RX statistics counters. If you turn on the Enforce Maximum Frame Size parameter, the IP core truncates incoming Ethernet packets that exceed this size.

In variations without MAC, this parameter has no effect and remains at the default value of 1518.

Enforce Maximum Frame Size
  • On
  • Off
 Off Specifies whether the IP core is able to receive an oversized packet or truncates these packets.
Choose Link Fault Generation Mode
  • OFF
  • Unidirectional
  • Bidirectional
 Bidirectional

Specifies the IP core response to link fault events.

Bidirectional link fault handling complies with the Ethernet specification, specifically IEEE 802.3 Figure 81-11. Unidirectional link fault handling implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets. The OFF option is provided for backward compatibility.

Stop TX traffic when link partner sends pause
  • Yes
  • No
  • Disable Flow Control
 No Selects whether the IP core responds to PAUSE frames from the Ethernet link by stopping TX traffic, or not. This parameter has no effect if flow control is disabled. If you disable flow control, the IP core neither responds to incoming PAUSE and PFC frames nor generates outgoing PAUSE and PFC frames.

If this parameter has the value of No, you can use the i_tx_pause signal on the TX client interface to force the TX MAC to stop TX traffic. Bytes to remove from RX frames

Bytes to remove from RX frames
  • None
  • Remove CRC bytes
  • Remove CRC and PAD bytes
 Remove CRC bytes You can set for the RX MAC to remove CRC and/or PAD bytes from incoming RX frames before passing the bytes to the RX MAC Client. If the PAD and CRC bytes are not needed downstream, the remove option can reduce the need for downstream packet processing logic.
Forward RX Pause Requests
  • On
  • Off
 Off Selects whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface, or drops them after internal processing.
Note: If flow control is turned off, the IP core forwards all incoming PAUSE and PFC frames directly to the RX client interface and performs no internal processing. In that case this parameter has no effect.
Use Source Address Insertion
  • On
  • Off
 Off Selects whether the IP core supports overwriting the source address in an outgoing Ethernet packet with the value in the TXMAC_SADDR registers at offsets 0x40C and 0x40D. If the parameter is turned on, the IP core overwrites the packet source address from the register if i_tx_skip_crc has the value of 0. If the parameter is turned off, the IP core does not overwrite the source address.

Source address insertion applies to PAUSE and PFC packets provided on the TX MAC client interface, but does not apply to PAUSE and PFC packets the IP core transmits in response to the assertion of i_tx_pause or i_tx_pfc[n] on the TX MAC client interface.

Enable TX VLAN Detection
  • On
  • Off
 On Specifies whether the IP core TX statistics block treats TX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the TxFrameOctetsOK counter at offsets 0x862 and 0x863. If turned on, the IP core identifies these frames in TX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.
Enable RX VLAN Detection
  • On
  • Off
 On Specifies whether the IP core RX statistics block treats RX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the RxFrameOctetsOK counter at offsets 0x962 and 0x963. If turned on, the IP core identifies these frames in RX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.
Ready latency 0-3 0

Selects the readyLatency value on the TX client interface. readyLatency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the o_sl_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon Interface Specifications.

In PCS Only, OTN, and FlexE variations, this parameter has no effect.

Selecting a longer latency (higher number) eases timing closure at the expense of increased latency for the TX datapath in MAC+PCS variations.

Enable asynchronous adapter clocks 5
  • On
  • Off
 Off Turn on if you want to drive TX/RX interface using clock source different from i_sl_clk_rx/i_sl_clk_tx. The different clock source is driven through another clock port (i_sl_async_clk_rx/i_sl_async_clk_tx).

Supported clock frequency range is between 390.625 MHz and 402.83203125 MHz.

MAC Options: Specialized 10GE/25GE

Note: In PCS Only, OTN, and FlexE variations, these parameters have no effect.

Enable preamble passthrough

  • On
  • Off

Off

If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.

Enable strict preamble check
  • On
  • Off

Off

 If turned on, the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55).

This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

Enable strict SFD check
  • On
  • Off

Off

 If turned on, the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5).

This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

Average Inter-packet Gap
  • 1
  • 8
  • 10
  • 12

12

Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link.Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link.

The default value of 12 complies with the Ethernet standard.

The remaining values support increased throughput.

The value of 1 specifies that the IP core transmits Ethernet packets as soon as the data is available, with the minimum possible gap. The IPG depends on the space you leave between frame data as you write it to the core. The IP core no longer complies with the Ethernet standard but the application has control over the average gap and maximizing the throughput. For more information, refer to the Inter-Packet Gap Generation and Insertion section.

Additional IPG removed per AM period Integer

0

 Specifies the number of inter-packet gaps the IP core removes per alignment marker period, in addition to the default number required for protocol compliance.

Each increment of 1 in the value of Additional IPG removed per AM period increases throughput by 3ppm in 100G variations. To specify larger throughput increases, use the Average Inter-packet Gap parameter.

PMA Options 10GE/25E

PHY Reference Frequency
  • 156.25 MHz
  • 322.265625 MHz
  • 312.5 MHz 6
  • 644.53125 MHz 6

322.265625 MHz

Sets the expected incoming PHY i_clk_ref reference frequency. The input clock frequency must match the frequency you specify for this parameter (±100 ppm).

Note: If you turn on Enable AN/LT, the required input clock frequency are 156.25 or 312.5 MHz.
Enable custom rate
  • On
  • Off

Off

Turn on to enable custom rate.
Note: This parameter is not available when Enable SyncE is turned on.
Include refclk_mux
  • On
  • Off

Off

Turn on to increase the number of allowed reference clocks. The reference clocks connect to the channel's input.

By default, all channels are connected to the refclk[0] reference clock. To reassign a channel to a different reference clock, program the refclk_mux_sel register.

Include deterministic latency measurement interface
  • On
  • Off
Off This feature is available for internal use only.
Table 17.   E-Tile Hard IP for Ethernet Intel FPGA IP Parameters: 100GE TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.

Parameter

Range

Default Setting

Parameter Description

General Options
Select Ethernet Rate 100G

100G

Selects the IP core Ethernet data rate.
Select Ethernet IP Layers
  • MAC+PCS
  • MAC+PTP+PCS
  • MAC+PCS+(528,514) RS-FEC
  • MAC+PCS+(544,514) RS-FEC
  • MAC+PTP+PCS+(528,514) RS-FEC
  • PCS Only
  • PCS+(528,514) RS-FEC
  • PCS+(544,514) RS-FEC
  • OTN
  • OTN+(528,514) RS-FEC
  • OTN+(544,514) RS-FEC
  • FlexE
  • FlexE+(528,514) RS-FEC
  • FlexE+(544,514) RS-FEC
 MAC+PCS

Selects the Ethernet Protocol layers provided by the channel.

Note: The E-Tile Hard IP for Ethernet Intel FPGA IP provides support for the OTN feature. For further inquiries, contact your nearest Intel sales representative.

MAC Options: Basic 100GE

Note: In PCS Only, OTN, and FlexE variations, these parameters have no effect.
TX Maximum Frame Size 65–65535 1518 Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters.

In variations without MAC, this parameter has no effect and remains at the default value of 1518.

RX Maximum Frame Size 65–65535 1518 Maximum packet size (in bytes) the IP core can receive on the Ethernet link without reporting an oversized packet in the RX statistics counters. If you turn on the Enforce Maximum Frame Size parameter, the IP core truncates incoming Ethernet packets that exceed this size.

In variations without MAC, this parameter has no effect and remains at the default value of 1518.

Enforce Maximum Frame Size
  • On
  • Off
 Off Specifies whether the IP core is able to receive an oversized packet or truncates these packets.
Choose Link Fault Generation Mode
  • OFF
  • Unidirectional
  • Bidirectional
 Bidirectional

Specifies the IP core response to link fault events.

Bidirectional link fault handling complies with the Ethernet specification, specifically IEEE 802.3 Figure 81-11. Unidirectional link fault handling implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets. The OFF option is provided for backward compatibility.

Stop TX traffic when link partner sends pause
  • Yes
  • No
  • Disable Flow Control
 No Selects whether the IP core responds to PAUSE frames from the Ethernet link by stopping TX traffic, or not. This parameter has no effect if flow control is disabled. If you disable flow control, the IP core neither responds to incoming PAUSE and PFC frames nor generates outgoing PAUSE and PFC frames.

If this parameter has the value of No, you can use the i_tx_pause signal on the TX client interface to force the TX MAC to stop TX traffic.

Bytes to remove from RX frames
  • None
  • Remove CRC bytes
  • Remove CRC and PAD bytes
 Remove CRC bytes You can set for the RX MAC to remove CRC and/or PAD bytes from incoming RX frames before passing the bytes to the RX MAC Client. If the PAD and CRC bytes are not needed downstream, the remove option can reduce the need for downstream packet processing logic.
Forward RX Pause Requests
  • On
  • Off
 Off Selects whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface, or drops them after internal processing.
Note: If flow control is turned off, the IP core forwards all incoming PAUSE and PFC frames directly to the RX client interface and performs no internal processing. In that case this parameter has no effect.
Use Source Address Insertion
  • On
  • Off
 Off Selects whether the IP core supports overwriting the source address in an outgoing Ethernet packet with the value in the TXMAC_SADDR registers at offsets 0x40C and 0x40D. If the parameter is turned on, the IP core overwrites the packet source address from the register if i_tx_skip_crc has the value of 0. If the parameter is turned off, the IP core does not overwrite the source address.

Source address insertion applies to PAUSE and PFC packets provided on the TX MAC client interface, but does not apply to PAUSE and PFC packets the IP core transmits in response to the assertion of i_tx_pause or i_tx_pfc[n] on the TX MAC client interface.

Enable TX VLAN Detection
  • On
  • Off
 On Specifies whether the IP core TX statistics block treats TX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the TxFrameOctetsOK counter at offsets 0x862 and 0x863. If turned on, the IP core identifies these frames in TX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.
Enable RX VLAN Detection
  • On
  • Off
 On Specifies whether the IP core RX statistics block treats RX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the RxFrameOctetsOK counter at offsets 0x962 and 0x963. If turned on, the IP core identifies these frames in RX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.
Enable asynchronous adapter clocks
  • On
  • Off
 Off Turn on if you want to drive i_clk_rx and i_clk_tx clocks from different clock sources.
Note: For 100GbE, the asynchronous adapter clocks are only available when PTP is disabled.
Ready latency 0-3 0

Selects the readyLatency value on the TX client interface. readyLatency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the o_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon Interface Specifications. This feature only supports MAC+PCS variant.

In PCS Only, OTN, and FlexE variations, this parameter has no effect. Selecting other variations produces an error.

Selecting a longer latency (higher number) eases timing closure at the expense of increased latency for the TX datapath in MAC+PCS variations.

MAC Options: Specialized 100GE

Note: In PCS Only, OTN, and FlexE variations, these parameters have no effect.

Enable preamble passthrough

  • On
  • Off

Off

If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.

Enable strict preamble check
  • On
  • Off

Off

 If turned on, the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55).

This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

Enable strict SFD check
  • On
  • Off

Off

 If turned on, the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5).

This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

Average Inter-packet Gap
  • 1
  • 8
  • 10
  • 12

12

Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link.Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link.

The default value of 12 complies with the Ethernet standard.

The remaining values support increased throughput.

The value of 1 specifies that the IP core transmits Ethernet packets as soon as the data is available, with the minimum possible gap. The IPG depends on the space you leave between frame data as you write it to the core. The IP core no longer complies with the Ethernet standard but the application has control over the average gap and maximizing the throughput. For more information, refer to the Inter-Packet Gap Generation and Insertion section.

Additional IPG removed per AM period Integer

0

 Specifies the number of inter-packet gaps the IP core removes per alignment marker period, in addition to the default number required for protocol compliance. In 100G variations, the default number is 20.

Each increment of 1 in the value of Additional IPG removed per AM period increases throughput by 3ppm in 100G variations. To specify larger throughput increases, use the Average Inter-packet Gap parameter.

PMA Options 100GE

Preserve Unused Transceiver Channels 7
  • On
  • Off

Off

 Preserves the unused PAM4 slave channel when you select variant with (544,514) RS-FEC option.
Reference Clock Frequency for Preserved Channels

125 MHz to 500 MHz

125 MHz

 When the Preserve Unused Transceiver Channels is enabled, the IP core adds additional reference clock to the preserve unused PAM4 channel. Set the reference clock value within the available frequency range.
PHY Reference Frequency
  • 156.25 MHz
  • 322.265625 MHz
  • 312.5 MHz
  • 644.53125 MHz

156.25 MHz

Sets the expected incoming PHY i_clk_ref reference frequency. The input clock frequency must match the frequency you specify for this parameter (±100 ppm).

Variants with (544,514) RS-FEC option only support 156.25 MHz and 312.5 MHz PHY i_clk_ref reference frequency.

Note: If you turn on Enable AN/LT, the required input clock frequency are 156.25 or 312.5 MHz.
Table 18.   E-Tile Hard IP for Ethernet Intel FPGA IP Parameters: Custom PCS Channel(s) TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.

Parameter

Range

Default Setting

Parameter Description

PCS Core Options
Number of PCS Channels in core
  • 1
  • 2
  • 3
  • 4
 1 Set the number of PCS channels you want to implement.

Resources such as RS-FEC and PTP are more efficient if shared. If your design requires multiple channels, consider increasing the number of channels in the core to share resources more efficiently.

PCS General Options
Custom PCS mode
  • PCS_Only
  • PCS+RS-FEC
 PCS_Only

Selects the Ethernet Protocol layers provided by the channel.

RSFEC Fibre Channel(s) mode
  • Disable
  • Enable
 Disable To enable or disable RS-FEC Fibre Channel mode for custom PCS.
Custom PCS Rate 2500 to 28000 Mbps 2500 Mbps Specifies the transceiver TX data rate in megabits per second (Mbps) unit.
PMA Options
PMA modulation type NRZ NRZ Specifies the type of modulation for TX serial data.
PMA reference clock frequency
  • 500.000000
  • 312.500000
  • 277.777777
  • 250.000000
  • 227.272727
  • 208.333333
  • 192.307692
  • 178.571428
  • 166.666666
  • 156.250000
  • 147.058823
  • 138.888888
  • 131.578947
  • 125.000000
 250.000000 Sets the custom PCS reference clock frequency.
Enable custom rate regulation
  • On
  • Off
   Turn on this option to add the custom rate ports to your design. You are required to drive the ports with an appropriate flow regulation signal.

For parameters in the PMA Adaptation tab, refer to the PMA Adaptation topic in the E-Tile Transceiver PHY User Guide.

Related Information
4 Currently, the SyncE feature is not available in the Intel Stratix 10 E-tile Hardware Design Example.
5 In 10G variant, the asynchronous adapter clock is available only when PTP is enabled.
6 Not supported for 10G/25G mode. For more information refer to this knowledge base.
7 For more information about preserving unused transceiver channels in high-speed PAM4 mode, refer to the E-Tile Transceiver PHY User Guide.
Level Two Title